4,785 research outputs found

    Test beam Characterizations of 3D Silicon Pixel detectors

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    3D silicon detectors are characterized by cylindrical electrodes perpendicular to the surface and penetrating into the bulk material in contrast to standard Si detectors with planar electrodes on its top and bottom. This geometry renders them particularly interesting to be used in environments where standard silicon detectors have limitations, such as for example the radiation environment expected in an LHC upgrade. For the first time, several 3D sensors were assembled as hybrid pixel detectors using the ATLAS-pixel front-end chip and readout electronics. Devices with different electrode configurations have been characterized in a 100 GeV pion beam at the CERN SPS. Here we report results on unirradiated devices with three 3D electrodes per 50 x 400 um2 pixel area. Full charge collection is obtained already with comparatively low bias voltages around 10 V. Spatial resolution with binary readout is obtained as expected from the cell dimensions. Efficiencies of 95.9% +- 0.1 % for tracks parallel to the electrodes and of 99.9% +- 0.1 % at 15 degrees are measured. The homogeneity of the efficiency over the pixel area and charge sharing are characterized.Comment: 5 pages, 7 figure

    LArPix: Demonstration of low-power 3D pixelated charge readout for liquid argon time projection chambers

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    We report the demonstration of a low-power pixelated readout system designed for three-dimensional ionization charge detection and digital readout of liquid argon time projection chambers (LArTPCs). Unambiguous 3D charge readout was achieved using a custom-designed system-on-a-chip ASIC (LArPix) to uniquely instrument each pad in a pixelated array of charge-collection pads. The LArPix ASIC, manufactured in 180 nm bulk CMOS, provides 32 channels of charge-sensitive amplification with self-triggered digitization and multiplexed readout at temperatures from 80 K to 300 K. Using an 832-channel LArPix-based readout system with 3 mm spacing between pads, we demonstrated low-noise (<<500 e^- RMS equivalent noise charge) and very low-power (<<100 μ\muW/channel) ionization signal detection and readout. The readout was used to successfully measure the three-dimensional ionization distributions of cosmic rays passing through a LArTPC, free from the ambiguities of existing projective techniques. The system design relies on standard printed circuit board manufacturing techniques, enabling scalable and low-cost production of large-area readout systems using common commercial facilities. This demonstration overcomes a critical technical obstacle for operation of LArTPCs in high-occupancy environments, such as the near detector site of the Deep Underground Neutrino Experiment (DUNE).Comment: 19 pages, 10 figures, 1 ancillary animation. V3 includes minor revisions based on referee comment

    Radiation hardness of small-pitch 3D pixel sensors up to HL-LHC fluences

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    A new generation of 3D silicon pixel detectors with a small pixel size of 50×\times50 and 25×\times100 μ\mum2^{2} is being developed for the HL-LHC tracker upgrades. The radiation hardness of such detectors was studied in beam tests after irradiation to HL-LHC fluences up to 1.4×10161.4\times10^{16} neq_{\mathrm{eq}}/cm2^2. At this fluence, an operation voltage of only 100 V is needed to achieve 97% hit efficiency, with a power dissipation of 13 mW/cm2^2 at -25^{\circ}C, considerably lower than for previous 3D sensor generations and planar sensors.Comment: 5 pages, 2 figures, Proceedings of TIPP 2017, Beijing (International Conference on The Technology and Instrumentation in Particle Physics 2017

    Compact, directional neutron detectors capable of high-resolution nuclear recoil imaging

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    We report on the design, production, and performance of compact 40-cm3 Time Projection Chambers (TPCs) that detect fast neutrons by measuring the three-dimensional (3D) ionization distribution of nuclear recoils in 4He:CO2 gas at atmospheric pressure. We use these detectors to characterize the fast-neutron flux inside the Belle II detector at the SuperKEKB electron–positron collider in Tsukuba, Japan, where the primary design constraint is a small form factor. We find that the TPCs meet or exceed all design specifications, and are capable of measuring the 3D surface shape and charge density profile of ionization clouds from nuclear recoils and charged tracks in exquisite detail. Scaled-up detectors based on the detection principle demonstrated here may be suitable for directional dark matter searches, measurements of coherent neutrino–nucleus scattering, and other experiments requiring precise detection of neutrons or nuclear recoils

    HV/HR-CMOS sensors for the ATLAS upgrade—concepts and test chip results

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    In order to extend its discovery potential, the Large Hadron Collider (LHC) will have a major upgrade (Phase II Upgrade) scheduled for 2022. The LHC after the upgrade, called High-Luminosity LHC (HL-LHC), will operate at a nominal leveled instantaneous luminosity of 5× 1034 cm−2 s−1, more than twice the expected Phase I . The new Inner Tracker needs to cope with this extremely high luminosity. Therefore it requires higher granularity, reduced material budget and increased radiation hardness of all components. A new pixel detector based on High Voltage CMOS (HVCMOS) technology targeting the upgraded ATLAS pixel detector is under study. The main advantages of the HVCMOS technology are its potential for low material budget, use of possible cheaper interconnection technologies, reduced pixel size and lower cost with respect to traditional hybrid pixel detector. Several first prototypes were produced and characterized within ATLAS upgrade R&#38;D effort, to explore the performance and radiation hardness of this technology. In this paper, an overview of the HVCMOS sensor concepts is given. Laboratory tests and irradiation tests of two technologies, HVCMOS AMS and HVCMOS GF, are also given

    Low power discriminator for ATLAS pixel chip

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    The design of the front-end (FE) pixel electronics requires low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the presence of a signal at the input of the discriminator. Since the activity in the FE chip is very low, the power consumption is largely reduced allowing the material reduction in the B-layer

    The Layer 0 Inner Silicon Detector of the D0 Experiment

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    This paper describes the design, fabrication, installation and performance of the new inner layer called Layer 0 (L0) that was inserted in the existing Run IIa Silicon Micro-Strip Tracker (SMT) of the D0 experiment at the Fermilab Tevatron collider. L0 provides tracking information from two layers of sensors, which are mounted with center lines at a radial distance of 16.1 mm and 17.6 mm respectively from the beam axis. The sensors and readout electronics are mounted on a specially designed and fabricated carbon fiber structure that includes cooling for sensor and readout electronics. The structure has a thin polyimide circuit bonded to it so that the circuit couples electrically to the carbon fiber allowing the support structure to be used both for detector grounding and a low impedance connection between the remotely mounted hybrids and the sensors.Comment: 28 pages, 9 figure
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