25 research outputs found

    A fully integrated 2:1 self-oscillating switched-capacitor DC-DC converter in 28 nm UTBB FD-SOI

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    The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have multiple power modes. Achieving high conversion efficiency within the DC–DC converter that supplies these processors is critical since energy consumption of the DC–DC/processor system is proportional to the DC–DC converter efficiency. The DC–DC converter must maintain high efficiency over a large load range generated from the multiple power modes of the processor. This paper presents a fully integrated step-down self-oscillating switched-capacitor DC–DC converter that is capable of meeting these challenges. The area of the converter is 0.0104 mm2 and is designed in 28 nm ultra-thin body and buried oxide fully-depleted SOI (UTBB FD-SOI). Back-gate biasing within FD-SOI is utilized to increase the load power range of the converter. With an input of 1 V and output of 460 mV, measurements of the converter show a minimum efficiency of 75% for 79 nW to 200 µW loads. Measurements with an off-chip NT processor load show efficiency up to 86%. The converter’s large load power range and high efficiency make it an excellent fit for energy-constrained processors.</p

    Vegetation impacts ditch methane emissions from boreal forestry-drained peatlands—Moss-free ditches have an order-of-magnitude higher emissions than moss-covered ditches

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    Ditches of forestry-drained peatlands are an important source of methane (CH4) to the atmosphere. These CH4 emissions are currently estimated using the IPCC Tier 1 emission factor (21.7 g CH4 m(-2) y(-1)), which is based on a limited number of observations (11 study sites) and does not take into account that the emissions are affected by the condition and age of the ditches. Furthermore, the total area of different kinds of ditches remains insufficiently estimated. To constructmore advanced ditch CH4 emission factors for Finland, we measured CH4 emissions in ditches of 3 forestry-drained peatland areas (manual chamber technique) and amended this dataset with previously measured unpublished and published data from 18 study areas. In a predetermined 2type ditch classification scheme, the mean CH4 emissions (+/- standard error) were 2.6 +/- 0.8 g CH4 m(-2) y(-1) and 20.6 +/- 7.0 g CH4 m(-2) y(-1) in moss-covered and moss-free ditches, respectively. In a more detailed 4-type classification scheme, the yearly emissions were 0.6 +/- 0.3, 3.8 +/- 1.1, 8.8 +/- 3.2, and 25.1 +/- 9.7 g CH4 m(-2) y(-1) in Sphagnum-covered, Sphagnum-and vascular plant-covered, moss-free and vascular plant-covered, and plant -free ditches, respectively. Hence, we found that Tier 1 emission factor may overestimate ditch CH4 emissions through overestimation of the emissions of moss-covered ditches, irrespective of whether they harbor potentially CH4 conducing vascular plants. Based on the areal estimates and the CH4 emission factors for moss-covered and moss-free ditches, CH4 emissions of ditches of forestry-drained peatlands in Finland were 8,600 t a(-1), which is 63% lower than the current greenhouse gas inventory estimates for ditch CH4 emissions (23,200 t a(-1)). We suggest that the Tier 1 emission factor should be replaced with more advanced emission factors in the estimation of ditch CH4 emissions of boreal forestry-drained peatlands also in other countries than in Finland. Furthermore, our results suggest that the current practice in Finland to minimize ditch-network maintenance by ditch cleaning will likely decrease CH4 emissions from ditches, since old moss-covered ditches have very low emissions.Peer reviewe

    A robust ultra-low voltage CPU utilizing timing-error prevention

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    To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing.</p

    Neuromorfismin soveltaminen piirisuunnitteluun

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    Luonnon tietojenkäsittelyjärjestelmät - aivot ja hermosto - ovat energiatehokkuudeltaan ja vikasietoisuudeltaan erinomaisia. Nämä ominaisuudet ovat usein tärkeinä tavoitteina myös keinotekoisissa järjestelmissä. Tässä työssä haluttiin tutkia luonnon keinoja päästä edellämainittuihin ominaisuuksiin, sekä sitä, kuinka saatua tietoa voidaan soveltaa piirisuunnitteluun. Asian selvittämiseksi kartoitettiin nykyisen tietämyksen tasoa neuromorfismista ja sen nykyisiä sovellutuksia. Lisäksi selvitettiin lähtökohtia tiedon soveltamiseksi piirisuunnitteluun, ja suunniteltiin neuromorfinen piirirakenne. Neuromorfismin sovellutuksia ja mahdollisuuksia pohdittiin myös yleisellä tasolla. Työssä on käsitelty informaatioteoriaa ja sen merkitystä neuromorfismin soveltamisessa, pohdittu energiankulutusta, esitelty hermoston ja aivojen toimintaa, sekä mietitty lähtökohtia lähentää keinotekoista tietojenkäsittelyä biologisen vastineensa kanssa. Rinnakkaistaminen ja alhaisen laskentatarkkuuden käyttäminen ovat eräitä luonnon keino- ja alhaisen energiankulutuksen ja vikasietoisuuden saavuttamiseksi. Rinnakkaistamisen etujen toteamiseksi suunniteltiin rinnakkaisiin ADA-lohkoihin pohjautuva kokonaisuus. Järjestelmän toimintaa analysoitiin sekä matemaattisesti että simuloinneilla. Suunniteltu ADA-järjestelmä toteutettiin 0,35 µm CMOS-teknologialla käyttäen hyväksi kelluvahilaisia transistoreja ja kynnysjännitteen alapuolista toiminta-aluetta

    Kirkniemen paperitehtaan jätevesipäästökartoitus

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    Energy efficiency through neuromorphism

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    Energy efficiency through neuromorphism

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    FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?

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    Timing error detection in ultra dynamic voltage scaling systems

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    Adaptive subthreshold timing-error detection 8 bit microcontroller in 65 nm CMOS

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