Feasibility studies of the time-like proton electromagnetic form factor measurements with PANDA at FAIR

The possibility of measuring the proton electromagnetic form factors in the time-like region at FAIR with the \PANDA detector is discussed. Detailed simulations on signal efficiency for the annihilation of $\bar p +p$ into a lepton pair as well as for the most important background channels have been performed. It is shown that precision measurements of the differential cross section of the reaction $\bar p +p \to e^++ e^-$ can be obtained in a wide angular and kinematical range. The individual determination of the moduli of the electric and magnetic proton form factors will be possible up to a value of momentum transfer squared of $q^2\simeq 14$ (GeV/c)$^2$. The total $\bar p +p\to e^++e^-$ cross section will be measured up to $q^2\simeq 28$ (GeV/c)$^2$. The results obtained from simulated events are compared to the existing data. Sensitivity to the two photons exchange mechanism is also investigated.Comment: 12 pages, 4 tables, 8 figures Revised, added details on simulations, 4 tables, 9 figure

Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization

Abstract. For mobile embedded systems, the energy consumption is a limiting factor because of today’s battery capacities. Besides the processor, memory accesses consume a high amount of energy. The use of additional less power hungry memories like caches or scratchpads is thus common. This paper presents a combined approach for energy consumption minimization consisting of two complementary and phase-coupled optimizations, viz. data partitioning and loop nest splitting. In a first step, data partitioning partitions large arrays found in typical embedded software into smaller ones which are placed onto an on-chip scratchpad memory. Although being effective w. r. t. energy dissipation, this optimization adds overhead to the code since the correct part of a partitioned array has to be selected at runtime. Therefore, the control flow is optimized as a second step in our framework. In this phase, loop nests containing if-statements are split using genetic algorithms leading to minimized if-statement executions. However, loop nest splitting leads to an increase in code size and can potentially annul the program layout achieved by the first step. Consequently, the proposed approach iteratively applies these optimizations till a local optimum is found. The proposed framework of combined memory and control flow optimization leads to considerable energy savings for a representative set of typical embedded software routines. Using an accurate energy model for the ARM7 processor, energy savings between 20.3 % and 43.3 % were measured.

Improving data locality by chunking

Abstract. Cache memories were invented to decouple fast processors from slow memories. However, this decoupling is only partial, and many researchers have attempted to improve cache use by program optimization. Potential benefits are significant since both energy dissipation and performance highly depend on the traffic between memory levels. But modeling the traffic is difficult; this observation has led to the use of heuristic methods for steering program transformations. In this paper, we propose another approach: we simplify the cache model and we organize the target program in such a way that an asymptotic evaluation of the memory traffic is possible. This information is used by our optimization algorithm in order to find the best reordering of the program operations, at least in an asymptotic sense. Our method optimizes both temporal and spatial locality. It can be applied to any static control program with arbitrary dependences. The optimizer has been partially implemented and applied to non-trivial programs. We present experimental evidence that the amount of cache misses is drastically reduced with corresponding performance improvements.

Design Space Exploration for Massively Parallel Processor Arrays

In this paper, we describe an approach for the optimization of dedicated co-processors that are implemented either in hardware (ASIC) or configware (FPGA). Such massively parallel co-processors are typically part of a heterogeneous hardware/software-system. Each coprocessor is a massive parallel system consisting of an array of processing elements (PEs). In order to decide whether to map a computational intensive task into hardware, existing approaches either try to optimize for performance or for cost with the other objective being a secondary goal