Bias Resilient Multi-Step Off-Policy Goal-Conditioned Reinforcement Learning

In goal-conditioned reinforcement learning (GCRL), sparse rewards present significant challenges, often obstructing efficient learning. Although multi-step GCRL can boost this efficiency, it can also lead to off-policy biases in target values. This paper dives deep into these biases, categorizing them into two distinct categories: "shooting" and "shifting". Recognizing that certain behavior policies can hasten policy refinement, we present solutions designed to capitalize on the positive aspects of these biases while minimizing their drawbacks, enabling the use of larger step sizes to speed up GCRL. An empirical study demonstrates that our approach ensures a resilient and robust improvement, even in ten-step learning scenarios, leading to superior learning efficiency and performance that generally surpass the baseline and several state-of-the-art multi-step GCRL benchmarks.Comment: 26 pages, 7 figure

Design of millimeter-wave transmitter in silicon-based technologies

University of Technology Sydney. Faculty of Engineering and Information Technology.Nowadays, with rapid advances being made in wireless communications, the demand for high-performance radio frequency (RF) transmitters has risen dramatically. An increasing number of challenges are evident for radio frequency integrated circuit (RFIC) designers while the operational frequency is being pushed to millimeter-wave (mmWave). The transmitter is an electronic device that can be used to send radio signals. A typical transmitter may contain many components, such as an RF power amplifier and a switch. The efficiency of the transmitter can significantly guide the performance of the whole wireless system. For this reason, it is necessary for RFIC researchers to propose more efficient designs. Therefore, in this thesis, the design methodologies of a high-performance mmWave power amplifier and two silicon-based single-pole double-throw (SPDT) switches are presented. The first approach is used to design a symmetrical 90 GHz single-pole double-throw switch in CMOS Technology. To improve the power-handling capability of bulk CMOS-based single-pole double-throw (SPDT) switch, a novel design approach that combines both power dividing and impedance transformation techniques is used to improve 1-dB compression point (P1dB). The SPDT switch is implemented in a 55nm bulk CMOS technology and achieves a measured P1dB of 15 dBm and an insertion loss of 3.5 dB and an isolation of 17 dB. The die area is only 0.14 mm^2. In the second work, to further improve the power-handling capability of the SPDT switch, a 90-GHz asymmetrical SPDT switch is designed. Taking advantage of utilizing a unique passive ring structure, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. The design has achieved an IL of 3.2 dB and 3.6 dB in Transceiver (TX) and Receiver (RX) mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. The P1dB is 19.5dBm. The die area of this design is only 0.26 mm^2. In the third work, a wideband millimeter-wave (mm-Wave) power amplifier (PA) is designed. To ensure the designed PA has sufficient output power and good power-added efficiency (PAE), a balanced amplifier (BA) architecture is used. A prototype PA is fabricated in a 0.13-μm SiGe HBT technology. Supplied by 5V power, the PA can provide more than 15 dBm saturated output power between 85-100 GHz that is equivalent to more than 16% fractional bandwidth. The peak PAE is better than 14% within this frequency range. Including all pads, the die area is only 0.6 mm × 0.9 mm

Diseño y experimentos de alivio de carga

Diseñar, implementar y evaluar experimentos de alivio de carga durante el proceso de marcha, sin agregar peso al voluntario, agregando peso adicional y con dicho peso aplicar alivio de carga con la máquina robótica IBWS de la facultad de ingeniería electrónica.Design, implement and evaluate the load relief experiments during the running process, without adding the weight to the volunteer, adding the additional weight and with that weight applying the load of the robotic machine of the faculty of electronic engineering.Ingeniero (a) ElectrónicoPregrad

Vibration-Induced Elastic Deformation of Fabry-Perot Cavities

We perform a detailed numerical analysis of Fabry-Perot cavities used for state-of-the-art laser stabilization. Elastic deformation of Fabry-Perot cavities with various shapes and mounting methods is quantitatively analyzed using finite-element analysis. We show that with a suitable choice of mounting schemes it is feasible to minimize the susceptibility of the resonator length to vibrational perturbations. This investigation offers detailed information on stable optical cavities that may benefit the development of ultrastable optical local oscillators in optical atomic clocks and precision measurements probing the fundamental laws of physics

A 40-GHz Load Modulated Balanced Power Amplifier using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS

© 2023 IEEE - All rights reserved. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCSI.2023.3282731 ​​​​​​​In this work, a ten-way power-combined poweramplifier is designed using a load modulated balanced amplifier(LMBA)-based architecture. To provide the required magnitudeand phase controls between the main and control-signal paths ofthe LMBA, an unequal power splitter and a phase compensationnetwork are proposed. As proof of concept, the designed poweramplifier is implemented in a 45-nm SOI CMOS process. At 40GHz, it delivers a 25.1 dBm Psat with a peak power-addedefficiency (PAE) of 27.9%. At 6-dB power back-off level, itachieves 1.39 times drain efficiency enhancement over an idealClass-B power amplifier. Using a 200-MHz single-carrier 64-QAMsignal, the designed amplifier delivers an average output power of16.5 dBm with a PAE of 13.1% at an EVMrms of -23.9 dB andACPR of -25.3 dBc. The die size, including all testing pads, is only1.92 mm2. To the best of the authors’ knowledge, compared withthe other recently published silicon-based LMBAs, this designachieves the highest Psat.Peer reviewe

A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS

© 2022 IEEE -This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/LMWC.2022.3159529Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm2.Peer reviewe