Rapid IoT Prototyping: A Visual Programming Tool and Hardware Solutions for LoRa-Based Devices

LoRa technology has gained popularity as one of the most widely used standards for device interconnection due to its ability to cover long distances and energy efficiency, making it a suitable choice for various Internet of Things (IoT) monitoring and control applications. In this sense, this work presents the development of a visual support tool for creating IoT devices with LoRa and LoRaWAN connectivity. This work significantly advances the state of the art in LoRa technology by introducing a novel visual support tool tailored for creating IoT devices with LoRa and LoRaWAN connectivity. By simplifying the development process and offering compatibility with multiple hardware solutions, this research not only facilitates the integration of LoRaWAN technology within educational settings but also paves the way for rapid prototyping of IoT nodes. The incorporation of block programming for LoRa and LoRaWAN using the Arduinoblocks framework as a graphical environment enhances the capabilities of the tool, positioning it as a comprehensive solution for efficient firmware generation. In addition to the visual tool for firmware generation, multiple compatible hardware solutions enable easy, economical, and stable development, offering a comprehensive hardware and software solution. The hardware proposal is based on an ESP32 microcontroller, known for its power and low cost, in conjunction with an RFM9x module that is based on SX127x LoRa transceivers. Finally, three successfully tested use cases and a discussion are presented

Academic Use of Rapid Prototyping in Digitally Controlled Power Factor Correctors

The growing use of power converters connected to the grid motivates their study in power electronics courses and the prototype development in the degree final project (DFP). However, the practical realization of using state-of-the-art components and conversion techniques is complex due to the numerous multidisciplinary aspects that students must consider in its design and development and the workload associated with the DFP. An example of this is that, unlike a conventional power factor correction (PFC) design, the individual dedication of students to complete the design and validation of modern bridgeless PFC stages exceeds the number of credits of the DFP. The reason for this is that it includes system modeling, becoming familiar with the devices used, discrete selection, circuit design, control development, and programming, to build the converter and verify the operation of the complete system. To reinforce the individual skills needed for the DFP and reduce this time, a novel strategy is proposed. It allows the student to focus their efforts on integrating the individual skills achieved in the degree at the appropriate competence level during the modeling and construction of the power converter while carrying out part of the tasks out of the lab, if necessary, as was the case during the pandemic restrictions. For this, the rapid prototyping technique is introduced to speed up the overall design and speed up the tuning of digital controllers. This manuscript presents a teaching experience in which students build digitally controlled power converters using Texas Instruments microcontroller boards and PLECS®. The example of a bridgeless totem-pole power factor corrector is shown. Although it began to develop and was motivated due to the restrictions during the COVID-19 pandemic, the experience has been verified and is maintained over time, successfully consolidating

Academic use of rapid prototyping in digitally controlled power factor correctors

The growing use of power converters connected to the grid motivates their study in power electronics courses and the prototype development in the degree final project (DFP). However, the practical realization of using state-of-the-art components and conversion techniques is complex due to the numerous multidisciplinary aspects that students must consider in its design and development and the workload associated with the DFP. An example of this is that, unlike a conventional power factor correction (PFC) design, the individual dedication of students to complete the design and validation of modern bridgeless PFC stages exceeds the number of credits of the DFP. The reason for this is that it includes system modeling, becoming familiar with the devices used, discrete selection, circuit design, control development, and programming, to build the converter and verify the operation of the complete system. To reinforce the individual skills needed for the DFP and reduce this time, a novel strategy is proposed. It allows the student to focus their efforts on integrating the individual skills achieved in the degree at the appropriate competence level during the modeling and construction of the power converter while carrying out part of the tasks out of the lab, if necessary, as was the case during the pandemic restrictions. For this, the rapid prototyping technique is introduced to speed up the overall design and speed up the tuning of digital controllers. This manuscript presents a teaching experience in which students build digitally controlled power converters using Texas Instruments microcontroller boards and PLECS®. The example of a bridgeless totem-pole power factor corrector is shown. Although it began to develop and was motivated due to the restrictions during the COVID-19 pandemic, the experience has been verified and is maintained over time, successfully consolidating.This research was funded by the Spanish Ministry of Science and Innovation under Project PID2021-128941OB-I00 TRENTI–Efficient Energy Transformation in Industrial Environment

Two-sample PLL with harmonic filtering capability applicable to single-phase grid-connected converters

The two-sample phase locked loop (2S PLL) in single-phase digitally controlled grid-connected power converters provide synchronization with a minimal computational burden. However, the distortion of the grid voltage deteriorates the performance of the 2S quadrature signal generator. To solve this issue, this article introduces a harmonic filtering (HF) structure based on observers of the input voltage for the fundamental and selected harmonics. The stability and sensitivity of the 2S PLL with HF is analyzed. In comparison with second-order generalized integrator (SOGI)-based HF, the observers provide a narrower bandpass, and the subsequent deterioration of the response time is compensated by adapting the filter gains dynamically. The results obtained, both in simulation and experimentally, validate the proposal and compare its performance with other widely adopted PLLs providing harmonic rejection capability. The computational burden is analyzed and in the case of the proposals depends on the number of observers and the use or not of the adaptive strategy based on steepest descent.This work has been supported by the Spanish Ministry of Science and Innovation under Project RTI2018-095138-B-C31 PEGIA Power Electronics for the Grid and Industry Applications

Evaluation of quadrature signal generation methods with reduced computational resources for grid synchronization of single-phase power converters through phase-locked loops

Low-cost single-phase grid connected converters require synchronization with the grid voltage to obtain a better response and protection under diverse conditions, such as frequency perturbations and distortion. Phase-locked loops (PLLs) have been used in this scenario. This paper describes a set of quadrature signal generators for single-phase PLLs; compares the performances by means of simulation tests considering diverse operation conditions of the electrical grid; proposes strategies to reduce the computational burden, considering fixed-point digital implementations; and provides both descriptive and quantitative comparisons of the required mathematical operations and memory units for implementation of the analyzed single-phase PLLs.This work has been supported by the Spanish Ministry of Science and Innovation under Project RTI2018-095138-B-C31 PEGIA—Power Electronics for the Grid and Industry Applications

Improved noise immunity for two-sample PLL applicable to single-phase PFCs

Synchronization in a single-phase Power Factor Correction (PFC) is deteriorated, among others, by the combination of the noise introduced by the grid voltage sensing, conducted EMI, the ADC resolution and the sampling frequency used. Low signal-to-noise ratios (SNR) reduce the performance of the Two-Sample (2S) Phase Locked Loop (PLL). This effect can be compensated by including a smoothing filter action without increasing the overall complexity significantly. The resulting 2S with smoothing (2SS) is evaluated and validated by simulation and experimentally over a Totem Pole PFC.This work has been supported by the Spanish Ministry of Science and Innovation under Project RTI2018-095138-BC31 PEGIA - Power Electronics for the Grid and Industry Applications

Frequency estimation in DSOGI cells by means of the teager energy operator

Second Order Generalized Integrator (SOGI) cells are used for notch filtering due to their simplicity and their harmonic rejection capability. SOGI and Dual SOGI (DSOGI) filter cells, combined with Frequency Locked Loops (FLL) to adjust the notch frequency, are commonly used in both 1f and 3f grid following (GFL) power converters for synchronization, i.e. SOGI-FLL and DSOGI-FLL, respectively. The FLL relies on a gradient descent method to minimize a cost function built up around one inner SOGI cell variable, e.g., the in-quadrature voltage estimation, and one outer variable, i.e. the error signal due to the SOGI filter cell. As a result, the FLL manages relatively large DC offsets and harmonic distortion passing through the outer SOGI cell variable, which deteriorates the frequency estimation and then, the SOGI-FLL performance. To attenuate such issues, the method proposed in this digest only uses inner SOGI cell variables. It minimizes the deviation between the estimated grid frequency and the frequency of the signal across the SOGI cell, which is detected through the Teager Energy Operator (TEO). The proposal is validated in simulation and experimentally.This work has been supported by the Ministry of Science and Innovation through the project RTI2018-095138-B-C31:"Electrónica de potencia aplicada a la red eléctrica y a procesos industriales": PEGIA

Two-sample PLL with improved frequency response applied to single-phase current sensorless bridgeless PFCs

A new implementation of the recently proposed fixed-frequency two-sample (2S) quadrature generation subsystem (QSG) digital Phase Locked Loop PLL, applicable to single-phase Power Factor Correction (PFC), is proposed. Its characteristics are high accuracy and low computational burden. The proposed PLL includes a frequency feedback loop to improve the synchronization under line frequency variations. Its performance within a digital controller of a current sensorless bridgeless PFC is evaluated by simulations and experimentally. The obtained results are compared with previously published PLLs in the literature.This work has been supported by the Spanish Ministry of Economy and Competitiveness under grant TEC2014-52316-R ECOTREND Estimation and Optimal Control for Energy Conversion with Digital Devices

Performance analysis of 1ϕ T/4 PLLs with secondary control path in current sensorless bridgeless PFCs

New power factor correction (PFC) stages such as bridgeless converters and the associated current shaping techniques require grid synchronization to ensure unity Displacement Power Factor (DPF). Sensorless line current rebuilding algorithms also need synchronization with the line voltage to compensate at least for part of the current estimation error. The application of a secondary control path to reach faster and more robustly the proper operation point previously applied in single/three-phase PLLs in grid connected converters is here proposed for the current sensorless bridgeless PFCs. This work analyzes the performance of three single-phase T/4 PLL structures, first without secondary control path, and later with feedforward and feedback secondary control paths, both in simulation and experimentally, and evaluates their applicability to current sensorless digitally controlled single phase bridgeless PFCs based on the current rebuilding technique.This work has been supported by the Spanish Ministry of Economy and Competitiveness under grant TEC2014-52316-R ECOTREND Estimation and Optimal Control for Energy Conversion with Digital Devices

Envelope-based modeling for single-phase grid-following and forming converters

The study of the interaction with the grid, including synchronization, controller design and stability assessment for 1o grid-following (GFL) and grid-forming (GFM) power converters requires an efficient modeling tool to design universal grid-connected converters considering the different grid scenarios. From the initial time-periodic system, approximated linear time-invariant (LTI) models are obtained through dynamic phasors, linearization of variables represented in a virtual synchronous rotating reference frame (RRF) or linearization in the frequency domain, i.e. harmonic linearization. The accuracy and complexity of the obtained model depend on the method used. This work proposes to use the well-known envelope modeling approach used for resonant converters but requiring the time periodic input to generate its related phase synchronization for the model. The result is a simple and accurate LTI model of 1º GFL/GFM power converter for such stability studies. The proposed 1o modeling approach is valid for any application with phase locked loop (PLL) synchronization. Simulation results validating de proposal are provided.This work has been supported by the Ministry of Science and Innovation through the project RTI2018-095138-B-C31:"Electrónica de potencia aplicada a la red eléctrica y a procesos industriales": PEGI