Generalized disjunction decomposition for the evolution of programmable logic array structures

Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+ë) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on Programmable Logic Array (PLA) structures

Generalized disjunction decomposition for evolvable hardware

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the “generalized disjunction decomposition” (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the$(1 + lambda)$evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided

Optimal softening for force calculations in collisionless N-body simulations

In N-body simulations the force calculated between particles representing a given mass distribution is usually softened, to diminish the effect of graininess. In this paper we study the effect of such a smoothing, with the aim of finding an optimal value of the softening parameter. As already shown by Merritt (1996), for too small a softening the estimates of the forces will be too noisy, while for too large a softening the force estimates are systematically misrepresented. In between there is an optimal softening, for which the forces in the configuration approach best the true forces. The value of this optimal softening depends both on the mass distribution and on the number of particles used to represent it. For higher number of particles the optimal softening is smaller. More concentrated mass distributions necessitate smaller softening, but the softened forces are never as good an approximation of the true forces as for not centrally concentrated configurations. We give good estimates of the optimal softening for homogeneous spheres, Plummer spheres, and Dehnen spheres. We also give a rough estimate of this quantity for other mass distributions, based on the harmonic mean distance to the $k$th neighbour ($k$ = 1, .., 12), the mean being taken over all particles in the configuration. Comparing homogeneous Ferrers ellipsoids of different shapes we show that the axial ratios do not influence the value of the optimal softening. Finally we compare two different types of softening, a spline softening (Hernquist & Katz 1989) and a generalisation of the standard Plummer softening to higher values of the exponent. We find that the spline softening fares roughly as well as the higher powers of the power-law softening and both give a better representation of the forces than the standard Plummer softening.Comment: 16 pages Latex, 19 figures, accepted for publication in MNRAS, corrected typos, minor changes mainly in sec.

A novel genetic algorithm for evolvable hardware

Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system. However, evolvable hardware is not widely recognized as a tool for solving real-world applications, because of the scalability problem, which limits the size of the system that may be evolved. In this paper a new genetic algorithm, particularly designed for evolving logic circuits, is presented and tested for its scalability. The proposed algorithm designs and optimizes logic circuits based on a Programmable Logic Array (PLA) structure. Furthermore it allows the evolution of large logic circuits, without the use of any decomposition techniques. The experimental results, based on the evolution of several logic circuits taken from three different benchmarks, prove that the proposed algorithm is very fast, as only a few generations are required to fully evolve the logic circuits. In addition it optimizes the evolved circuits better than the optimization offered by other evolutionary algorithms based on a PLA and FPGA structures

Superconductivity-Induced Anderson Localisation

We have studied the effect of a random superconducting order parameter on the localization of quasi-particles, by numerical finite size scaling of the Bogoliubov-de Gennes tight-binding Hamiltonian. Anderson localization is obtained in d=2 and a mobility edge where the states localize is observed in d=3. The critical behavior and localization exponent are universal within error bars both for real and complex random order parameter. Experimentally these results imply a suppression of the electronic contribution to thermal transport from states above the bulk energy gap.Comment: 4 pages, revtex file, 3 postscript figure

Forming disk galaxies in wet major mergers. I. Three fiducial examples

Using three fiducial Nbody+SPH simulations, we follow the merging of two disk galaxies with a hot gaseous halo component each, and examine whether the merger remnant can be a spiral galaxy. The stellar progenitor disks are destroyed by violent relaxation during the merging and most of their stars form a classical bulge, while the remaining form a thick disk and its bar. A new stellar disk forms subsequently and gradually in the remnant from the gas accreted mainly from the halo. It is vertically thin and well extended in its equatorial plane. A bar starts forming before the disk is fully in place, contrary to what is assumed in idealised simulations of isolated bar-forming galaxies. It has morphological features such as ansae and boxy/peanut bulges. Stars of different ages populate different parts of the box/peanut. A disky pseudobulge forms also, so that by the end of the simulation, all three types of bulges coexist. The oldest stars are found in the classical bulge, followed by those of the thick disk, then by those in the thin disk. The youngest stars are in the spiral arms and the disky pseudobulge. The disk surface density profiles are of type II (exponential with downbending), and the circular velocity curves are flat and show that the disks are submaximum in these examples: two clearly so and one near-borderline between maximum and submaximum. On average, only roughly between 10 and 20% of the stellar mass is in the classical bulge of the final models, i.e. much less than in previous simulations.Comment: 17 pages, 8 figures, accepted for publication in ApJ. V2: replaced Figure 4 with correct versio

On evolution of relatively large combinational logic circuits

Evolvable hardware (EHW) (Yao and Higuchi, 1999) is a technique introduced to automatically design circuits where the circuit configuration is carried out by evolutionary algorithms. One of the main difficulties in using EHW to solve real-world problems is the scalability. Until now, several strategies have been proposed to avoid this problem, but none of them completely tackle the issue. In this paper three different methods for evolving the most complex circuits have been tested for their scalability. These methods are bi-directional incremental evolution (SO-BIE); generalised disjunction decomposition (GD-BIE) and evolutionary strategies (ES) with dynamic mutation rate. In order to achieve the generalised conclusions the chosen approaches were tested using multipliers, traditionally used in EHW, but also logic circuits taken from MCNC (Yang, 1991) benchmark library and randomly generated circuits. The analysis of the approaches demonstrated that PLA-based ES is capable of evolving logic circuits of up to 12 inputs. The use of SO-BIE allows the generation of fully functional circuits of 14 inputs and GD-BIE is estimated to be able to evolve circuits of 21 inputs

Analysis of genotype size for an evolvable hardware system

The evolution of logic circuits, which falls under the heading of evolvable hardware, is carried out by evolutionary algorithms. These algorithms are able to automatically configure reconfigurable devices. One of main difficulties in developing evolvable hardware with the ability to design functional electrical circuits is to choose the most favourable EA features such as fitness function, chromosome representations, population size, genetic operators and individual selection. Until now several researchers from the evolvable hardware community have used and tuned these parameters and various rules on how to select the value of a particular parameter have been proposed. However, to date, no one has presented a study regarding the size of the chromosome representation (circuit layout) to be used as a platform for the evolution in order to increase the evolvability, reduce the number of generations and optimize the digital logic circuits through reducing the number of logic gates. In this paper this topic has been thoroughly investigated and the optimal parameters for these EA features have been proposed. The evolution of logic circuits has been carried out by an extrinsic evolvable hardware system which uses (1+lambda) evolution strategy as the core of the evolution