Investigation of the RTN Distribution of nanoscale MOS devices from subthreshold to on-state

This letter presents a numerical investigation of the statistical distribution of the random telegraph noise (RTN) amplitude in nanoscale MOS devices, focusing on the change of its main features when moving from the subthreshold to the on-state conduction regime. Results show that while the distribution can be well approximated by an exponential behavior in subthreshold, large deviations from this behavior appear when moving toward the on-state regime, despite a low probability exponential tail at high RTN amplitudes being preserved. The average value of the distribution is shown to keep an inverse proportionality to channel area, while the slope of the high-amplitude exponential tail changes its dependence on device width, length, and doping when moving from subthreshold to on-state

Phase change materials in non-volatile storage

After revolutionizing the technology of optical data storage, phase change materials are being adopted in non-volatile semiconductor memories. Their success in electronic storage is mostly due to the unique properties of the amorphous state where carrier transport phenomena and thermally-induced phase change cooperate to enable high-speed, low-voltage operation and stable data retention possible within the same material. This paper reviews the key physical properties that make this phase so special, the quantitative framework of cell performance, and the future perspectives of phase-change memory devices at the deep nanoscale

Performance optimization of detector electronics for millimeter laser ranging

The front-end electronic circuitry plays a fundamental role in determining the performance actually obtained from ultrafast and highly sensitive photodetectors. We deal here with electronic problems met working with microchannel plate photomultipliers (MCP-PMTs) and single photon avalanche diodes (SPADs) for detecting single optical photons and measuring their arrival time with picosecond resolution. The performance of available fast circuits is critically analyzed. Criteria for selecting the most suitable electronics are derived and solutions for exploiting the detector performance are presented and discussed

A Multi-Channel Low-Power System-on-Chip for in vivo NeuralSpike Recording

This paper reports a multi-channel neural spike recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 64-channel low-power low-noise analog front-end, a single 8-bit analog-todigital converter (ADC), followed by digital signal compression and transmission units. The 400-MHz transmitter employs a Manchester-Coded Frequency Shift Keying (MC-FSK) modulator with low modulation index. In this way a 1.25-Mbit/s data rate is delivered within a band of about 3 MHz. Compression of the raw data is implemented by detecting the action potentials (APs) and storing 20 samples for each spike waveform. The choice greatly improves data quality and allows single neuron identification. A larger than 10-m transmission range is reached with an overall power consumption of 17.2 mW. This figure translates into a power budget of 269 μW per channel, which is in line with the results in literature but allowing a larger transmission distance and more efficient wireless link bandwidth occupation. The implemented IC was mounted on a small and light printed circuit board to be used during neuroscience experiments with freely-behaving rats. Powered by 2 AAA batteries the system can work continuously for more than 100 hours allowing long-lasting neural spike recordings

An efficient tool for the assisted design of SAR ADCs capacitive DACs

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10^4 shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics

Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters

This work aims at estimating and comparing the power limits of ΔΣ and charge-redistribution successiveapproximation register (CR-SAR) analog-to-digital converters (ADCs), in order to identify which topology is the most powerefficient for a target resolution. A power consumption model for mismatch-limited SAR ADCs and for discrete-time (DT) ΔΣ modulators is presented and validated against experimental data. SAR ADCs are found to be the best choice for low-to-medium resolutions, up to roughly 80 dB of dynamic range (DR). At high resolutions, on the other hand, ΔΣ modulators become more power-efficient. This is due to the intrinsic robustness of the ΔΣ modulation principle against circuit imperfections and nonidealities. Furthermore, a comparison of the area occupation of such topologies reveals that, at high resolutions and for a given dynamic range, ΔΣ ADCs result more area-efficient as well

Characterisation Studies of Silicon Photomultipliers

This paper describes an experimental setup that has been developed to measure and characterise properties of Silicon Photomultipliers (SiPM). The measured SiPM properties are of general interest for a multitude of potential applications and comprise the Photon Detection Efficiency (PDE), the voltage dependent cross-talk and the after-pulse probabilities. With the described setup the absolute PDE can be determined as a function of wavelength covering a spectral range from 350 to 1000nm. In addition, a method is presented which allows to study the pixel uniformity in terms of the spatial variations of sensitivity and gain. The results from various commercially available SiPMs - three HAMAMATSU MPPCs and one SensL SPM - are presented and compared.Comment: 11 pages, 21 figures, submitted to Nuclear Instruments and Methods in Physics Research Section

Possible link between Hashimoto's thyroiditis and oral lichen planus: a novel association found

none5Lo Muzio L.; Santarelli A.; Campisi G.; Lacaita MG.; Favia G.Lo Muzio, L.; Santarelli, Andrea; Campisi, G.; Lacaita, M. G.; Favia, G

A 64-Channel 965-μW Neural Recording SoC with UWB Wireless Transmission in 130-nm CMOS

This brief presents a 64-channel neural recording system-on-chip (SoC) with a 20-Mb/s wireless telemetry. Each channel of the analog front end consists of a low-noise bandpass amplifier, featuring a noise efficiency factor of 3.11 with an input-referred noise of 5.6 μVrms in a 0.001- to 10-kHz band and a 31.25-kSps 6-fJ/conversion-step 10-bit SAR analog-to-digital converter. The recorded signals are multiplexed in the digital domain and transmitted via an 11.7% efficiency pulse-position modulation ultrawideband transmitter, reaching a transmission range in excess of 7.5 m. The chip has been fabricated in a 130-nm CMOS process, measures 25 mm2, and dissipates 965 μW from a 0.5-V supply. This SoC features the lowest power per channel (15 μW) and the lowest energy per bit (48.2 pJ) among state-of-the-art wireless neural recording systems with a number of channels larger than 32. The proposed circuit is able to transmit the raw neural signal in a large bandwidth (up to 10 kHz) without performing any data compression or losing vital information, such as local field potentials

How to squeeze high quantum efficiency and high time resolution out of a SPAD

We address the issue whether Single-Photon Avalanche Diodes (SPADs) can be suitably designed to achieve a trade-off between quantum efficiency and time resolution performance. We briefly recall the physical mechanisms setting the time resolution of avalanche photodiodes operated in single-photon counting, and we give some criteria for the design of SPADs with a quantum efficiency better than l0 percent at 1064 nm together with a time resolution below 50 ps rms