On the uniqueness of the helicoid and Enneper’s surface in the Lorentz-Minkowski space R31

In this paper we deal with the uniqueness of the Lorentzian helicoid and Enneper’s surface among properly embedded maximal surfaces with lightlike boundary of mirror symmetry in the Lorentz-Minkowski space R3Ministerio de Ciencia y Tecnología MTM2004-00160Ministerio de Ciencia y Tecnología MTM2007-61775Junta de Andalucía P06-FQM-01642Junta de Andalucía FQM32

The procedure and the deceased´s goods files in the Casa de la Contratación de Indias (1503-1717)

El objetivo de este trabajo reside en dar a conocer el proceso que se utilizaba en la Casa de la Contratación de Sevilla para la entrega a los herederos de los bienes de aquellas personas que habían muerto en Indias. Un procedimiento que en la práctica se tradujo en la expedición ordenada de una serie de documentos que han llegado hasta nosotros en forma de expediente. Nuestro objetivo es presentar, desde una perspectiva diplomática, un análisis del funcionamiento de esta institución, como se refleja en estos expedientes, investigando las diferentes etapas en el procedimiento y sus posibles variantes.The objective of this work resides in giving to know the process used in the Casa de la Contratación de Sevilla to deliver to the heirs the goods of those who died in Indias. A procedure that was translated in the orderly expedition of a series of documents, which have arrived until us in file form. Our aim is to present, from a diplomatic perspective, an analysis of the functioning of this institution and as reflected in these dossiers, investigating the different stages in the procedure, besides the possible variants

An examination of different etiological pathways to alcohol use and misuse in adolescence

Treball Final de Màster Universitari en Investigació en Cervell i Conducta. Codi: SBM024. Curs: 2015/2016Alcohol abuse, especially among adolescents, causes important health, economic and social problems. Different theoretical pathways have been suggested for the etiology of alcohol use and abuse. The aim of our study was to describe some of these different etiological pathways in adolescents. We explored the importance and specific role of personality, cognitive variables (motives and drinking refusal self-efficacy under social pressure) and environmental variables (antinormative behavior of friends) in each etiological pathway. Method: We assessed in a sample of 201 high school students (47.3% females; mean age 15,41 years; SD = 1,124) the influence of these variables. Results: structural equation modelling showed the co-occurrence of 4 main etiological pathways: coping motives fully mediated the association between neuroticism and alcohol-related problems (negative affect regulation pathway), extraversion was linked to alcohol use at the weekend and alcohol-related problems through social drinking motives (positive affect regulation pathway), extraversion and low agreeableness was related to drinking at the weekend, alcohol-related problems and motives through anti-normative behavior of friends (deviance proneness pathway); finally, low extraversion, low neuroticism and conscientiousness was negatively associated with alcohol use and abuse through a greater drinking refusal self-efficacy in front of social pressure (force of will pathway). Conclusions: We observed the relevance of distal (personality domains) and more proximal variables (anti-normative behavior of friends, drinking refusal self-efficacy-social pressure and motives) in adolescent alcohol use and abuse, illustrating the complex interplay of these factors

The Admission Process for Ship’s Masters in the House of Trade: Files and Procedure

Los maestres fueron personajes clave en la Carrera de Indias. Por ello, la Casa de la Contratación los consideró responsables de cualquier infracción de las ordenanzas que se produjera a bordo de los barcos. Así, estaban obligados a presentar fiadores que respondieran por ellos y a cumplir otra serie de requisitos. Estos trámites se tradujeron en la expedición ordenada de una serie de documentos en la Casa de la Contratación, que han llegado a nosotros en forma de expedientes. El análisis de estos expedientes, desde el punto de vista de la Diplomática, es el principal objetivo de este trabajo.The masters were key figures in the Indies Run. For this reason, the House of Trade considered the masters responsible for any infraction of the ordinances that occurred on board the ships. In this way, masters were obliged to present guarantors who would vouch for them and meet others requirements. These procedures were translated in the orderly expedition of a series of documents in the House of Trade, which have arrived until us in the files form. The analysis of this files, from a diplomatic perspective, is the main objective of this work

Harmonic mappings and conformal minimal immersions of Riemann surfaces into RN

We prove that for any open Riemann surface N, natural number N ≥ 3, non-constant harmonic map h:N→R N−2 and holomorphic 2-form H on N , there exists a weakly complete harmonic map X=(Xj)j=1,…,\scN:N→R\scN with Hopf differential H and (Xj)j=3,…,\scN=h. In particular, there exists a complete conformal minimal immersion Y=(Yj)j=1,…,\scN:N→R\scN such that (Yj)j=3,…,\scN=h . As some consequences of these results (1) there exist complete full non-decomposable minimal surfaces with arbitrary conformal structure and whose generalized Gauss map is non-degenerate and fails to intersect N hyperplanes of CP\scN−1 in general position. (2) There exist complete non-proper embedded minimal surfaces in R\scN, ∀\scN>3.Ministerio de Ciencia y Tecnología MTM2007-61775Ministerio de Ciencia y Tecnología MTM2007-64504Junta de Andalucía P09-FQM-508

A Reuse-based framework for the design of analog and mixed-signal ICs

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.Ministerio de Educación y Ciencia TEC2004-0175

Geometrically-constrained, parasitic-aware synthesis of analog ICs

In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very time-consuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.Ministerio de Educación y Ciencia TEC2004-0175

The memory and the record of the Royal Treasury in Indies in the Casa de la Contratación.

Este artículo presenta, desde una perspectiva metodológica diplomática, la descripción y análisis de los libros de contabilidad que se llevaron en la Casa de la Contratación para el control administrativo y contable de la Real Hacienda. A estos efectos, mi objetivo es establecer el origen, naturaleza, formas y evolución, así como una clasificación de estos libros. Para el registro de las operaciones contables en esta institución se utilizaron, desde el momento de su creación en 1503, los libros de cargo y data. A mediados del siglo XVI aparecieron, además, los libros de arcas y los diarios y mayores de la partida doble.This paper present, from a diplomatic methodological perspective, a description and analysis the accounting books of the Casa de la Contratación to the administrative and accounting control of the Royal Treasury in Indies. To this purpose, it is possible to demonstrate the origin, nature, formals requirements and evolution, together with a classification of these books. Transactions were recorded in the charge and discharge books, since 1503, and since the mid-sixteenth century in the books about arks and in the journals and the ledgers for double-entry bookkeeping

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175