Lumped-Circuit Model Extraction for Vias in Multilayer Substrates

Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted in a systematic manner using this approach. A closed-form expression for via self inductance is further derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expression can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power-bus impedance as well as effective frequency range of decoupling capacitors

DC Power Bus Modeling in High-Speed Digital Designs Including Conductor and Dielectric Losses

Power bus design is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation formulation is presented herein to model arbitrary multilayer power bus structures including vertical discontinuities associated with surface mount (SMT) decoupling capacitor interconnects. Both conductor and dielectric losses are incorporated, and included into the first principles formulation. The agreement of modeling and measurements demonstrates its effectiveness and utilization in power bus designs

Modeling DC Power-Bus Structures with Vertical Discontinuities using a Circuit Extraction Approach Based on a Mixed-Potential Integral Equation

The DC power-bus is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation is presented herein to model arbitrary multilayer power-bus structures with vertical discontinuities that include decoupling capacitor interconnects. Green\u27s functions in a stratified medium are used and the problem is formulated using a mixed-potential integral equation approach. The final matrix equation is not solved, rather, an equivalent circuit model is extracted from the first-principles formulation. Agreement between modeling and measurements is good, and the utility of the approach is demonstrated for DC power-bus design

Quantifying Decoupling Capacitor Location

Decoupling capacitor location in DC power bus design is a critical design choice for which proven guidelines are not well established. The mutual inductance between two closely spaced vias can have a great impact on the coupling between an IC and a decoupling capacitor. This coupling is a function of the spacing between the IC and capacitor, and spacing between power and ground layers. The impact of the mutual inductance on decoupling, i.e., local versus global decoupling, was studied, using a circuit extraction approach based on a mixed-potential integral equation. Modeling indicates that local decoupling has benefits over global decoupling for certain ranges of IC/capacitor spacing and power layer thickness. Design curves for evaluating local decoupling benefits were generated, which can be used to guide surface mount technology (SMT) decoupling capacitor placement

The Design of a Lumped Element Impedance-Matching Network with Reduced Parasitic Effects Obtained From Numerical Modeling

This paper presents an impedance-matching network design with numerical modeling of the parasitic effects. A modeling tool CEMPIE (a Circuit Extraction approach based on a Mixed Potential Integral Equation formulation) is used to model the hoard-level parasitics of surface mount technology (SMT) resistors for impedance-matching networks. A 3-layer design of impedance-matching network with 0402 SMT resistors is implemented according to the modeling results. And its performance is demonstrated

Estimating the Noise Mitigation Effect of Local Decoupling in Printed Circuit Boards

Local decoupling, i.e., placing decoupling capacitors sufficiently close to device power/ground pins in order to decrease the impedance of power bus at frequencies higher than the series resonant frequency, has been studied using a modeling approach, a hybrid lumped/distributed circuit model established and an expression to quantify the benefits of power bus noise mitigation due to local decoupling developed. In this work, a test board with a local decoupling capacitor was studied and the noise mitigation effect due to the capacitor placed adjacent to an input test port was measured. Closed-form expressions for self and mutual inductances of vias are developed, so that the noise mitigation effect can then be estimated using the previously developed expression. The difference between the estimates and measurements is approximately 1 dB, which demonstrates the application of these closed-form expressions in the PCB power bus designs. Shared-via decoupling, capacitors sharing vias with device power/ground pins, is also modeled as an extreme case of local decoupling

Predictive Modeling of the Effects of Skew and Imbalance on Radiated EMI from Cables

This paper provides an approach for predicting the effects of skew and imbalance on radiated emission of cables inside a commercial 19-inch rack-based cabinet. Scattering parameters (S-parameters) for two sets of cable assembly are measured with a four-port vector network analyzer (VNA) and converted into mixed mode S-parameters. Time-domain input signals with different slew rates and different amount of skew are transferred into frequency-domain using fast Fourier transform (FFT). The spectra of radiation emission associated with different inputs are then estimated

Grounding of Heatpipe/Heatspreader and Heatsink Structures for EMI Mitigation

EMI problems caused by the presence of heatpipe/heatspreader and heatsink structures in a high-speed design are well known in engineering practice. High-frequency noise can be coupled from IC packages to an electrically conductive heatsink or heatspreader attached to the IC, which then is radiated, or the energy coupled to an enclosure cavity mode. This EMI coupling path was modeled with the finite-difference time-domain (FDTD) method, and a mitigation approach was investigated. Good agreement between measurements and FDTD modeling is demonstrated, indicating FDTD is a suitable tool for analysis and design. Then, several grounding schemes suitable for a heatsink or heatspreader were compared using FDTD modeling. The results indicate that sufficiently connecting the heatspreader or heatsink to the top layer of the PCB, even without further electrically connecting to the PCB ground plane, can result in appreciable EMI reduction. Good electrical connection of the heatsink or heatspreader to the PCB ground plane through an SMT-mount approach can achieve a 10-25 dB reduction for EMI attributable to the proposed coupling path

Application of Transmission Line Models to Backpanel Plated Through-Hole Via Design

This paper introduces an approach of using a plated through-hole (PTH) via transmission-line model in the design of a thick printed circuit board, such as a backpanel. Full wave FEM modeling of a section of backpanel containing a differential via pair was compared with a transmission model. Computed values of the differential transmission loss agreed within an acceptable range for engineering studies, yet the transmission line model results required less than 2% of the computation time that the full wave model required. Effects of via spacing, via diameter and trace thickness were also examined

Transmission Line Modeling of Vias in Differential Signals

Signal layer transitions in differential lines are modeled using both FDTD and equivalent circuit methods. The equivalent circuit is developed based on transmission-line reasoning regarding via behavior. Parameters of each transmission-line segment are obtained based on its corresponding physical geometry. The mixed-mode S-parameters from the equivalent circuit and the FDTD modeling are compared. Good agreement is demonstrated in the frequency range from 1 GHz to 20 GHz. The results indicate that vias in differential lines can be modeled as a transmission line for a quick and easy engineering estimation of the differential signal behavior in an environment of signal layer transitions