260 research outputs found

    Crypto Embedded System for Electronic Document

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    In this paper, a development of low-cost RSA-based Crypto Embedded System targeted for electronic document security is presented. The RSA algorithm is implemented in a re-configurable hardware, in this case Field Programmable Gate Array (FPGA). The 32-bit soft cores of AlteraÂ’s Nios RISC processor is used as the basic building blocks of the proposed complete embedded solutions. AlteraÂ’s SOPC Builder is used to facilitate the development of crypto embedded system, particularly in hardware/software integration stage. The use of Cryptographic Application Programming Interface (CAPI) to bridge the application and the hardware, and the associated communication layer in the embedded system is also discussed. The result obtained shows that the crypto embedded system provides a suitable compromise between the constraints of speed, space and required security level based on the specific demands of targeted applications

    A decision model for investment alternatives in highway systems.

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    Massachusetts Institute of Technology, Dept. of Civil Engineering. Thesis. 1972. Sc. D.MICROFICHE COPY ALSO AVAILABLE IN BARKER ENGINEERING LIBRARY.Vita.Bibliography: leaves 156-159.Sc.D

    Stochastic approach to the analysis of highway pavements.

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    Massachusetts Institute of Technology, Dept. of Civil Engineering. Thesis. 1971. M.S.MICROFICHE COPY ALSO AVAILABLE IN BARKER ENGINEERING LIBRARY.Bibliography: leaves 92-95.M.S

    Dynamic power dissipation formulation for application in dynamic programming buffer insertion algorithm

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    Buffer insertion is a very effective technique to reduce propagation delay in nano-metre VLSI interconnects. There are two techniques for buffer insertion which are: (1) closed-form solution and (2) dynamic programming. Buffer insertion algorithm using dynamic programming is more useful than the closed-form solution as it allows the use of multiple buffer types and it can be used in tree structured interconnects. As design dimension shrinks, more buffers are needed to improve timing performance. However, the buffer itself consumes power and it has been shown that power dissipation of buffers is significant. Although there are many buffer insertion algorithms that were able to optimize propagation delay with power constraint, most of them used the closed-form solution. Hence, in this paper, we present a formulation to compute dynamic power dissipation of buffers for application in dynamic programming buffer insertion algorithm. The proposed formulation allows dynamic power dissipation of buffers to be computed incrementally. The technique is validated by comparing the formulation with the standard closed-form dynamic power equation. The advantage of the proposed formulation is demonstrated through a series of experiments where it is applied in van Ginneken’s algorithm. The results show that the output of the proposed formulation is consistent with the standard closed-form formulation. Furthermore, it also suggests that the proposed formulation is able to compute dynamic power dissipation for buffer insertion algorithm with multiple buffer types

    Smart wearable stress monitoring device for autistic children

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    Vital sign monitoring is the process of recording human physiological signals in order to determine the mental stress level. High stress levels can prove tobe dangerous especially for certain individuals such as autistic children who are not able to express mounting levels of stress before it leads to a full anxiety attack. This paper presents the prototype design of a real-time embedded device that accurately measures heart rate and galvanic skin response (GSR) in a non-invasive and non-intrusive way which is then used by the intelligent decision making module that uses fuzzy logic to determine the stress level of the user. Such a device could be used with autistic children in order to give early warning of an impending anxiety attack and help adults to prevent it from happening. The prototype was designed using Arduino mega platform and tested with 35 clinical patients in three experimental settings targeted to induce low stress, medium stress and high stress response. Initial results have shown that the device is capable of detecting and displaying the various stress levels efficiently

    واقع حرية الرأي والتعبير في منصات التواصل الاجتماعي لدى المستخدم الفلسطيني

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    هدف المقال بيان أهمية توجيه دور منصات التواصل الاجتماعي في إبراز الحق في حرية التعبير عن الرأي لدى المستخدم الفلسطيني في ظل الاحتلال الإسرائيلي، عبر التداول الرقمي والسردية للأحداث في فلسطين، وما نتج عن ممارسة هذا الحق من تقييد للحريات، وفرض عقوبات، واعتقالات، واتهامات بحق المستخدمين والناشطين الفلسطينيين. واعتمدت الدراسة على المنهج الوصفي التحليلي؛ في وصف دور منصات التواصل الاجتماعي في الحديث عن القضية الفلسطينية، وفي حرية التعبير عن الرأي للمستخدم الفلسطيني في ظل الاحتلال الاسرائيلي، بالإضافة للوقوف على طبيعة استخدام هذه المنصات وما ينتج عنه من انتهاكات من قبل سلطات الاحتلال وإدارات شركات التواصل الاجتماعي من خلال المقابلات المعمقة. وخلصت الدراسة إلى أن هناك علاقة أساسية وتعاونية بين منصات التواصل الاجتماعي والاحتلال لتعزيز نفوذه على الفضاء الرقمي، إذ يعد الفضاء الرقمي من أحد أكثر الأماكن اشتباكا في الوقت الحالي كونه متنفسا بديلاً للمستخدمين، يواجه فيه المستخدمون الفلسطينيون درجة عالية من التقييد، والسيطرة، والرقابة على المحتوى الالكتروني، وبالتالي، أصبح هناك حاجة ملحة للتصدي لانتهاكات الحقوق الرقمية بوصفها تؤثر بشكل أو بآخر كحواجز أمام حرية التعبير، الأمر الذي أبرز الحاجة لحماية حرية الرأي والتعبير من خلال توجيه دور منصات التواصل الاجتماعي من قبل الناشطين الفلسطينيين للدعم في رصد وتوثيق انتهاكات حقوق الإنسان في فلسطين. The aim of the article is to explain the importance of directing the role of social media platforms in highlighting the right to freedom of expression of opinion among the Palestinian users under the Israeli occupation through digital circulation and narration of events in Palestine and the resulting restriction of freedoms and the imposition of penalties, arrests, and accusations against the exercise of this right. Palestinian users and activists. The study relied on the descriptive analytical approach in describing the role of social media platforms in talking about the Palestinian issue and in the freedom to express opinions for the Palestinian user under the Israeli occupation, in addition to identifying the nature of the use of these platforms and the resulting violations by the occupation authorities and the management of social media companies through in-depth interviews. The study concluded that there is a fundamental and cooperative relationship between social media platforms and the occupation to enhance its influence on the digital space, as the digital space is one of the most conflicted places at the present time as it is an alternative outlet for users, in which Palestinian users face a high degree of restriction, control, and censorship of content. Thus, there has become an urgent need to address violations of “digital rights” as they affect, in one way or another, barriers to freedom of expression, which highlighted the need to protect freedom of opinion and expression by directing the role of social media platforms by Palestinian activists to support in monitoring and documenting human rights violations in Palestin

    An FPGA-based quantum computing emulation framework based on serial-parallel architecture

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    Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial- parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits

    Gender classification: a convolutional neural network approach

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    An approach using a convolutional neural network (CNN) is proposed for real-time gender classification based on facial images. The proposed CNN architecture exhibits a much reduced design complexity when compared with other CNN solutions applied in pattern recognition. The number of processing layers in the CNN is reduced to only four by fusing the convolutional and subsampling layers. Unlike in conventional CNNs, we replace the convolution operation with cross-correlation, hence reducing the computational load. The network is trained using a second-order backpropagation learning algorithm with annealed global learning rates. Performance evaluation of the proposed CNN solution is conducted on two publicly available face databases of SUMS and AT&T. We achieve classification accuracies of 98.75% and 99.38% on the SUMS and AT&T databases, respectively. The neural network is able to process and classify a 32 × 32 pixel face image in less than 0.27 ms, which corresponds to a very high throughput of over 3700 images per second. Training converges within less than 20 epochs. These results correspond to a superior classification performance, verifying that the proposed CNN is an effective real-time solution for gender recognition

    Stochastic Computing Correlation Utilization in Convolutional Neural Network Basic Functions

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    In recent years, many applications have been implemented in embedded systems and mobile Internet of Things (IoT) devices that typically have constrained resources, smaller power budget, and exhibit "smartness" or intelligence. To implement computation-intensive and resource-hungry Convolutional Neural Network (CNN) in this class of devices, many research groups have developed specialized parallel accelerators using Graphical Processing Units (GPU), Field-Programmable Gate Arrays (FPGA), or Application-Specific Integrated Circuits (ASIC). An alternative computing paradigm called Stochastic Computing (SC) can implement CNN with low hardware footprint and power consumption. To enable building more efficient SC CNN, this work incorporates the CNN basic functions in SC that exploit correlation, share Random Number Generators (RNG), and is more robust to rounding error. Experimental results show our proposed solution provides significant savings in hardware footprint and increased accuracy for the SC CNN basic functions circuits compared to previous work

    Convolutional Neural Network for Face Recognition with Pose and Illumination Variation

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    Face recognition remains a challenging problem till today. The main challenge is how to improve the recognition performance when affected by the variability of non-linear effects that include illumination variances, poses, facial expressions, occlusions, etc. In this paper, a robust 4-layer Convolutional Neural Network (CNN) architecture is proposed for the face recognition problem, with a solution that is capable of handling facial images that contain occlusions, poses, facial expressions and varying illumination. Experimental results show that the proposed CNN solution outperforms existing works, achieving 99.5% recognition accuracy on AR database. The test on the 35-subjects of FERET database achieves an accuracy of 85.13%, which is in the similar range of performance as the best result of previous works. More significantly, our proposed system completes the facial recognition process in less than 0.01 seconds
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