In this paper, a development of low-cost RSA-based Crypto Embedded System targeted for electronic document security is presented. The RSA algorithm is implemented in a re-configurable hardware, in this case Field Programmable Gate

Array (FPGA). The 32-bit soft cores of AlteraÂ’s Nios RISC processor is used as the basic building blocks of the proposed complete embedded solutions. AlteraÂ’s SOPC Builder is used to facilitate the development of crypto embedded system, particularly in hardware/software integration stage. The use of Cryptographic Application Programming Interface (CAPI) to bridge the application and the hardware, and the associated communication layer in the embedded system is also discussed. The result obtained shows that the crypto embedded system provides a suitable compromise between the constraints of speed, space and required security level based on the specific demands of targeted applications

Ahmad, Illiasaak

Hani, Mohamed Khalil

M.Thamrin, Norashikin

English

Universiti Teknologi Malaysia Institutional Repository

Electrical and Electronics 263Crypto Embedded System for Electronic DocumentIlliasaak Ahmad1, Norashikin M . Thamrin1, Mohamed Khalil Hani11VLSI-ECAD Research Laboratory,Microelectronic and Computer Engineering Department (MiCE)Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Johor, MalaysiaTel: +60-7-5535223, Fax: +60-7-5566272, E-mail: ilyasak_ahmad@yahoo.com,norashikin.mthamrin@gmail.com, khalil@ fke.utm.myAbstractIn this paper, a development of low-cost RSA-based Crypto Embedded System targeted for electronic documentsecurity is presented. The RSA algorithm is implemented in a re-configurable hardware, in this case Field Programmable Gate Array (FPGA). The 32-bit soft cores of Altera’s Nios RISC processor is used as the basic building blocks of the proposedcomplete embedded solutions. Altera’s SOPC Builder is used to facilitate the development of crypto embedded system, particularly in hardware/software integration stage. The use of Cryptographic Application Programming Interface (CAPI) tobridge the application and the hardware, and the associated communication layer in the embedded system is also discussed.The result obtained shows that the crypto embedded system provides a suitable compromise between the constraints of speed,space and required security level based on the specific demands of targeted applications.Keywords:Embedded System, Public Key Cryptography, FPGA, HW/SW Co-design1. IntroductionCryptography has gained an important role in today’sinformation security problems. Security of the system can beenhanced if it is embedded in a re-configurable hardware.Such implementation is harder to tap, decompose, and attack,n general.iThe protocols in public key cryptography like RSA, El-Gamal, etc, are excellent examples for implementingHW/SW co-design concept. Public key cryptography isbased on the difficulty of factoring large numbers. Toincrease the operation speed, the algorithm is most oftenrealized as a hardware component based on a parallel arrayof processing elements [1][2]. The hardware structures aregenerally fast enough, but not suitable for algorithmsequencing and they cannot be adapted to algorithm changes.Software, on the other hand, adapts itself easily but it ismuch slower and less secure. Thus implementingcryptographic algorithms in re-configurable hardware/SOCoffers the best solution: it can consist of an embeddedrocessor, one or more coprocessors, and software.pIn this paper 1024-bit RSA algorithm is implemented.Due to hardware resource constraint, the encryption andverification modules are implemented as embedded code,while decryption and signing operations are performed inhardware. Chinese Remainder Theorem (CRT) is deployednot only to speed up decryption and signing operations, butlso to utilize the 512-bit RSA co-processor designed in [3].aThis paper is organized as follows: Section 2 covers thefundamental concept of RSA algorithm. The design of cryptoembedded system is discussed in Section 3. Section 4 looksat the verification of the crypto embedded system and itsperformance. We discuss, in brief, the use of CryptographicApplication Programming Interface (CAPI) as high-levelinterface to the crypto embedded system in Section 5. Fina ly, concluding remarks is presented in the final section. l2. Overview of RSA AlgorithmAs reported in [4], the most widely used public-keyalgorithm is RSA algorithm. This is due to the fact that, RSAcan provide both confidentiality and digital signatures usingthe key-pair and under the same mathematical operation.Figure 1(a), 1(b), and 1(c) summarize RSA algorithm.1.Generate 2 primes, p and q randomly, where p ? q 2.Calculate M, where M = p * q3.Calculate φ(M), where φ(M) = (p – 1)(q – 1)4.Generate E (public exponent) that fulfills1 < E < φ(M) and GCD (φ(M), E) = 15.Calculate D (private exponent), where D = E-1 Modφ(M)Figure 1(a). RSA Key-Pair GenerationPlaintext (P) <MCiphertext (C) = PE Mod MFigure 1(b). RSA Encryption/VerificationCiphertext (C)Plaintext (P) =CE Mod MFigure 1(c). RSA Decryption/SigningRegional Postgraduate Conference on Engineering and Science (RPCES 2006), Johore, 26-27 July264 Electrical and Electronics3. Design of Crypto Embedded System An important aspect in embedded system design ispartitioning the overall system into hardware and softwarecomponents. This involves the physical partitioning of functionality into hardware or software, and it is influencedby system requirement, availability of device resources, IPcore, and execution time. Figure 2 depicts the genericmbedded HW/SW design flow.eThe architecture of the crypto embedded system isshown in Figure 3. It has a processor core, on-chip memory,a co-processor, UART communication, and internal systembus. Nios [5], a 32-bit soft core from Altera, is used as theprocessor, while Avalon Bus [6] is used to enablecommunication between processor and RSA co-processor.The RSA co-processor is designed to perform the intensivepart of computation of RSA algorithm. Nios processor isused to implement the more control intensive,parameterizable portions of RSA algorithm like embeddedencryption module, and some parts of decryption module.SHA-1 has also been implemented in Nios (to be used withdigital signature operation).Requirements DefinitionSpecificationSystem ArchitectureDevelopmentSW Development° Application software° Compiler, etc° Operating SystemInterface Design° Software driver° Hardware interfaceHW Design° HW architecture design° HW synthesis° Physical designSystem ArchitectureDevelopmentFigure 2. Generic Embedded HW/SW Design FlowNios CPUEmbedded RSAEncryptionEmbedded RSADecryption CRTDevice DriverRSA Co-ProcessorRSA CoreAvalonInterfaceNios peripheralsEmbedded SHA-1AvalonBusFigure 3. System Architecture of Crypto Embedded System 3.1 Interfacing RSA Co-processor with Embedded ProcessorIn this work, 512-bit RSA co-processor designed in [3] toperform 1024-bit RSA operation is used. This co-processoris designed to handle intensive modular arithmeticcomputations. It is, however, beyond the scope of this papero discuss the implementation of this co-processor in detail.tTo interface this co-processor with Nios processor,Avalon Bus is used as the bus system. Avalon Bus is a simple bus architecture designed for connecting on-chipprocessor and peripherals together into a system on aprogrammable chip. It is an interface that specifies the port connections between master and slave components, and alsospecifies the timing by which the components communicate[6]. Avalon Bus transactions transfer a single byte, half-word, or word (8, 16, or 32-bits) between a master and slaveeripheral.pThe RSA co-processor used in this work uses Avalonslave transfer mode that accept Avalon bus transfer from master port, which is Nios processor.3.2 HW /SW  IntegrationTools are available to integrate the processor, co-processor,and peripherals to become a complete embedded system. Inthis work, we used Altera SOPC Builder [7]. See Figure 4for an illustration of SOPC Builder HW/SW integrationflow. It is the interest of this paper to explore in greaterdetails the Software Development portion of the flow. Hardware DevelopmentSOPC BuilderConfigure MastersSelect & ConfigurePeripherals , IPConnect BlocksGenerateMaster Lib raryPeripheral L ibrary° ED IF Netlis t° HDL Source File° TestbenchQuartus IISynthesis & F itting° User Design° O ther IPBlocksPhysica l DeviceSoftw are ToolsCompile rAssembler° User Code° Lib ra ries° RTOS° C Header F iles° Custom Libra ry° Peripheral DriversIP Modu lesSoftware DevelopmentHardwareConfiguration FileSoftware CodeFigure 4. SOPC Builder HW/SW integration flow [8]To generate the software development kit (SDK) for the embedded system, all the peripherals and IP core used mustbe added and configured, see Figure 5. The RSA Co-processor is added here as user-defined interface. The baseaddress of this co-processor is set to 0x0900900. Since AlteraApex EP20K20EFC484-2X development board is used, theclock frequency is set to 33.33 MHz. Other configurationparameters include assignment of interrupt priorities, and theit requirements of each peripheral.setup, hold and waOn the completion of generation process, SOPC Buildergenerates the hardware and software driver file calledexcalibur.h. Excalibur.h includes all the software interfacesfor all the blocks in the embedded system. Apart from that,excalibur.h also includes the address for all registers andmemories inside the SOPC Builder as well as associated software application programming interfaces (APIs) for IP blocks that include APIs. Figure 6(a) and 6(b) show theexcerpts taken from excalibur.h. 3.3 Embedded Software DevelopmentBased on the previous section, the SOPC builder generates acustom SDK. The SDK contains the memory map and datastructures for accessing hardware components in the system.Regional Postgraduate Conference on Engineering and Science (RPCES 2006), Johore, 26-27 JulyElectrical and Electronics 265It also provides routines for accessing the peripherals like UART. So this SDK can be used to communicate easily withundamental system components and custom IP cores.fApplication programming interfaces are developed using C language to control the RSA Co-processor operations. Theinterfaces are: • RSA_OperandM()• RSA_OperandE()• RSA_OperandR()• RSA_OperandX()• RSA_Ouput()• RSA_MonMult_vec()• Compute_R()Besides that, embedded code for encryption anddecryption with CRT are also coded. Figure 7 illustrates theAPIs and the embedded software.A device driver for the crypto embedded system is alsodeveloped to enable communication between cryptoembedded system and external world like personal computer.The flow of the device driver can be described as statediagram. See Figure 8.RSA512 User Interface Logic Avalon 0x00900900 0x0090093Fcpu Nios Processor AvalonFigure 5. Configuring Crypto Embedded System UsingSOPC Builder// Th e M em ory M ap#define  na_cpu ((void *) 0x00000000 ) // a lte ra_nios#define  na_cpu_base 0x00000000#define  na_uart ((np_uart *) 0x00000400 ) // a lte ra_ava lon_uart#define na_uart_base 0x00000400#define na_uart_ irq 26#define na_tim er ((np_ tim er *) 0x00000440 ) // a lte ra_ava lon_ tim er#define na_tim er_base 0x00000440#define na_tim er_ irq 25#define na_ex t_ ram ((void *) 0x00040000 ) // a lte ra_nios_dev_board_sram 32#define na_ex t_ ram _base 0x00040000#define na_ex t_ ram _end ((void *) 0x00080000 )#define na_ex t_ ram _size 0x00040000#define na_ex t_ flash ((void *) 0x00100000 ) // a lte ra_nios_dev_board_ flash#define na_ex t_ flash_base 0x00100000#define na_ex t_ flash_end ((void *) 0x00200000 )#define na_ex t_ flash_size 0x00100000#define na_R S A 512 ((np_usersocket *) 0x00900900 ) // a lte ra_ava lon_user_defined_ in te rface#define na_R S A 512_base 0x00900900Figure 6(a). Excerpt from excalibur.h: Memory Map// S tru ctures  an d  R outines F or Each  P erip hera l// N ios C P U  R ou tinesvo id  n r_ ins ta llcw pm anager(vo id ); // ca lled  au tom atica lly  a t by n r_se tup.svoid  n r_de lay (in t m illiseconds); // approx im ate tim ing  based  on  c lock speedvoid  n r_zero range (char *rangeS ta rt,in t rangeB y teC oun t);vo id  n r_jum ptorese t(vo id );// D e fau lt U A R T rou tinesvo id  n r_ txchar(in t c);vo id n r_ txchar2 (in t c , in t channe l);vo id  n r_ txs tr ing (char *s );in t n r_ rxchar(vo id );Figure 6(b). Excerpt from excalibur.h: APIsbigdigits.cLong integer operationsrsa.cRSA_OperandM()RSA_OperandE()RSA_OperandR()RSA_OperandX()RSA_Output()RSA_monMult-vec()Compute_R()sha1.hexcalibur.hrsa.hbigdigits.hrsa_driver.csha1.cRSA Co-processorPersonal ComputerFigure 7. APIs and Embedded CodeIdleCallExecuteReturnFunctioncallFunctionExecuteFunctionEndFunctionErrorFunctionreturnFigure 8. Device driver state diagram4. ResultTo evaluate and verify software/hardware modules in thissolution and its impact on the speed of the RSA operation,test application is developed. The test application is run onNios processor.The test vector is obtained from National Institute ofStandards and Technology (NIST) [9] and hard-coded in thetest program. For this test we have predefined the value ofpublic key to be ‘17’, and this value can be easily changedaccording to the user’s requirement later. Table 1 shows thetiming of the RSA operations (CRT is deployed in RSAdecryption).Table 1. Execution times of RSA on Altera APEXEP20K200EFC484-2X clocked at 33.33 MHzOperation Time (ms)Encryption (software) 10Decryption (software with CRT) 18338Decryption (hardware with CRT) 111Regional Postgraduate Conference on Engineering and Science (RPCES 2006), Johore, 26-27 July266 Electrical and ElectronicsThe result obtained here is also compared with ARM SecurCore [11], one of the commercial products available inthe market. Table 2 below summarizes the comparisons that are made. Based on that table, we can see that the resultobtained is quite competitive in terms of performance.Table 2. Comparison with commercial productSpecifications Our design ARM SecurCoreKeySize 1024 1024Clock 33.33 Mhz 20 MHzDecryption(with CRT) 111 ms 330 msEncryption(software)10 ms -5. Cryptographic Application ProgrammingInterface (CAPI) Modern embedded systems are built using varioustechniques that provide flexibility and reliability. One of themost important techniques centres on the use of applicationsrogramming interface.pAn application-programming interface (API) is basically a well-defined boundary between two system componentsthat isolates a specific process or a set of services. For example, it is quite common now for an application tointeract with e-mail service using e-mail API like MAPI(Microsoft), VIM (Lotus), and others. In such cases, the APIdefines a set of services that allow an application to retriever submit mail messages from or to the mail server.oA cryptographic application programming interface(CAPI), like other APIs, is an API specifically designed tosupport cryptographic functions. Technically, a CAPI wouldprovide and interface to a set of cryptographic services suchas encryption/decryption, digital signatures/verification, keygeneration, etc. Figure 9 depicts the relation between CAPInd crypto services.aA simple and easy to use CAPI called myCAPI isdeveloped for the crypto embedded system presented in thispaper. myCAPI  has a set of well-defined APIs that enableapplication developers integrate crypto embedded systemservices into their application. The list of available APIs isisted in Table 3.lIn addition to myCAPI, the crypto embedded systemservices can also be called-up through Microsoft CryptoAPIinterface [10]. This integration would benefit the application developers. Since Microsoft CryptoAPI has been defined as one of the standard CAPI, application that utilizes MicrosoftCAPI can access multiple cryptographic implementationsthrough a single interface, see Figure 9. 6. ConclusionIn this paper, the design of crypto embedded system targetedfor electronic document security has been presented. Thecrypto embedded system is implemented in re-configurablehardware, which is FPGA. Altera CAD tool, SOPC Builderis used to facilitate and demonstrate hw/sw design anddevelopment flow. The result obtained shows that the cryptoembedded system provides a suitable compromise betweenthe constraint of speed, space and required security levelbased on the specific demands of targeted applications.Table 3. myCAPI APIsAPI DescriptionutmGenKeyPair() Key-pair generationutmRSASigning() RSA digital signaturesutmRSAVerification() RSA digital signaturesverificationutmRSAEncryption() RSA encryptionutmRSADecryption() RSA decryptionCrypto Application 1Crypto Application 1 Crypto Application 1Crypto Application 2 Crypto Application 1Crypto Application 3CryptographicServiceManagerCryptographic Application Programming Interface (CAPI)SoftwareCryptoHardwareCryptoFigure 9. CAPI ArchitectureReferences[1] A. F. Tenca and C. K. Koc. A scalable architecture forMontgomery multiplication. In C.K. Koc and C. Paar,editors, Cryptographic Hardware and EmbeddedSystems, number 1717 in Computer Science, pages 94-108, Berlin, Germany, 1999. Springer Verlag.[2] M. Drutarovsk?, V. Fischer, and M. ?imka. TwoImplementation Methods of Scalable MontgomeryCoprocessor Embedded in Reconfigurable Hardware.Cryptographic Hardware and Embedded Systems 2003.[3]  Paniandi. A, 2005. A Hardware Implementation of RSACo-processor for Resource Constrained EmbeddedSystems. Master Dissertation, Faculty of Electrical Engineering, Uni. Teknologi Malaysia.[4]  B. Schneier. Applied Cryptography: Protocol, Algorithmand Source Code in C. 2nd Edition, John Wiley & Sons Inc, NY. 1996.Regional Postgraduate Conference on Engineering and Science (RPCES 2006), Johore, 26-27 JulyElectrical and Electronics 267[5] Nios Soft Core Embedded Processor,http://www.altera.com/nios[6] Avalon Bus Specification, http://www.altera.com/literature/manual/[7]  Altera SOPC Builder, http://www.altera.com/products/software/products/sopc/[8] Ekas, P; Jentz B, Fall 2003. Developing and integratingFPGA coprocessors. Embedded Computing Design.[9] Keller. S. S, 2004. The RSA Validation System (RSAVS). National Institute of Standards andTechnology (NIST). USA.[10] Microsoft Developer Network,http://msdn.microsoft.com/library/[11] ARM Products and Solutions – Core Type,http://www.arm.com/products/CPUs/securcore.htmlRegional Postgraduate Conference on Engineering and Science (RPCES 2006), Johore, 26-27 July

Crypto Embedded System for Electronic Document

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Crypto Embedded System for Electronic Document

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