Macro-Instruction Generation for Dynamic Logic Caching

This paper outlines the synthesis of macroinstructions for dynamically reprogrammable FPGAs so that they may be easily generated, placed, and garbage collected at run-time. An overview of a dynamic logic caching computer that uses these macroinstructions is given and their use within this environment discussed. The synthesis of macro-instructions is illustrated with a basic example. Finally, the current state of development of a logic cache based computing platform and compiler/simulator workframe is presented. 1 Introduction Dynamically reconfigurable gate arrays can be used to implement time-sliced coprocessors. By changing the configuration in the gate array's static RAM during run time, the coprocessor changes function during the execution of the program to provide hardware support on an as-needed basis. Thinking of the co-processor as a hardware cache, operating in much the same way as a memory cache, can provide several important benefits for fast prototyping. The logic cache c..