Mesoscopic approach to progressive breakdown in ultrathin SiO2 layers

The opening of a breakdown path across the ultrathin oxide layer in a metal-oxide-semiconductor structure caused by the application of electrical stress can be analyzed within the framework of the physics of mesoscopic conductors. Using the Landauer formula for a quantum point contact, the author is able to show that the saturation of the gate leakage current is linked to the progressive evolution of the constriction's conductance toward the ballistic transport regime. The possible physical mechanisms responsible for energy dissipation inside the breakdown path as well as the limitations of the proposed approach are discussed

On the Thermal Activation of Negative Bias Temperature Instability

The temperature dependence of negative bias temperature instability (NBTI) is investigated on 2.0nm SiO2 devices from temperatures ranging from 300K down to 6K with a measurement window of ~12ms to 100s. Results indicate that classic NBTI degradation is observed down to ~200K and rarely observed at temperatures below 140K in the experimental window. Since experimental results show the charge trapping component contributing to NBTI is thermally activated, the results cannot be explained with the conventionally employed elastic tunneling theory. A new mechanism is observed at temperatures below 200K where device performance during stress conditions improves rather than degrades with time, which is opposite to the classical NBTI phenomenon

Logarithmic behavior of degradation dynamics in metal--oxide semiconductor devices

In this paper the authors describe a theoretical simple statistical modelling of relaxation process in metal-oxide semiconductor devices that governs its degradation. Basically, starting from an initial state where a given number of traps are occupied, the dynamics of the relaxation process is measured calculating the density of occupied traps and its fluctuations (second moment) as function of time. Our theoretical results show a universal logarithmic law for the density of occupied traps $\bar{} \sim \phi (T,E_{F}) (A+B \ln t)$, i.e., the degradation is logarithmic and its amplitude depends on the temperature and Fermi Level of device. Our approach reduces the work to the averages determined by simple binomial sums that are corroborated by our Monte Carlo simulations and by experimental results from literature, which bear in mind enlightening elucidations about the physics of degradation of semiconductor devices of our modern life

Key issues and solutions for characterizing hot carrier aging of nano-meter scale nMOSFETs

Silicon bandgap limits the reduction of operation voltage when downscaling device sizes. This increases the electrical field within a device and hot carrier aging (HCA) is becoming an important reliability issue again for some CMOS technologies. For nano-devices, there are a number of challenges for characterizing their HCA: the random charge-discharge of traps in gate dielectric causes ‘within-a-device-fluctuation (WDF)’, making the parameter shift uncertain after a given HCA. This can introduce errors when extracting HCA time exponents and it will be shown that the lower envelope of the WDF must be used. Nano-devices also have substantial device-to-device variation (DDV) and multiple tests are needed for evaluating their standard deviation, σ, and mean value, µ. Repeating the time-consuming HCA tests is costly and a voltage-step-stress method is applied to reduce the number of tests by 80%. For a given number of devices under tests (DUTs), there is little information on the accuracy of the extracted σ and µ. We will develop a method to provide this information, based on the defect-centric model. For 40 DUTs with an average of 10 traps per device, the extracted µ and σ has an accuracy of ±14% and ±24% respectively with a 95% confidence

Interaction Between Hot Carrier Aging and PBTI Degradation in nMOSFETs: Characterization, Modelling and Lifetime Prediction

Modelling of the interaction between Hot Carrier Aging (HCA) and Positive Bias Temperature Instability (PBTI) has been considered as one of the main challenges in nanoscale CMOS circuit design. Previous works were mainly based on separate HCA and PBTI instead of Interacted HCA-PBTI Degradation (IHPD). The key advance of this work is to develop a methodology that enables accurate modelling of IHPD through understanding the charging/discharging and generation kinetics of different types of defects during the interaction between HCA and PBTI. It is found that degradation during alternating HCA and PBTI stress cannot be modelled by independent HCI/PBTI. Different stress sequence, i.e. HCA-PBTI-HCA and PBTI-HCA-PBTI, lead to completely different degradation kinetics. Based on the Cyclic Anti-neutralization Model (CAM), for the first time, IHPD has been accurately modelled for both short and long channel devices. Complex degradation mechanisms and kinetics can be well explained by our model. Our results show that device lifetime can be underestimated by one decade without considering interaction

Understanding the Excess 1/f Noise in MOSFETs at Cryogenic Temperatures

Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature ( $\textit{T}$ ), referred to as “excess 1/f noise”, observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures

NBTI of Ge pMOSFETs: understanding defects and enabling lifetime prediction

Ge pMOSFETs are strong candidates for next technology nodes and record hole mobility has been reported for Al2O3/GeO2/Ge and HfO2/SiO2/Si-cap/Ge structures. Reliability, however, is still problematic and currently impedes the progress. Large NBTI exists in GeO2/Ge, and little is known about the defects. Si-cap/Ge device has superior reliability, but its lifetime, τ, cannot be predicted by power law extrapolation. This work demonstrates that the defects are different in Ge and Si devices. For the first time, a method is developed for Ge devices to restore the power law for NBTI kinetics, which enables τ prediction and process optimization

Development of a Technique for Characterizing Bias Temperature Instability-Induced Device-to-Device Variation at SRAM-Relevant Conditions

SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse-(I) -(V) , random telegraph noises, time-dependent defect spectroscopy, and TDDV accounting for the within-device fluctuation. These techniques, however, cannot be directly applied to SRAM, because their test conditions do not comply with typical SRAM operation. The central objective of this paper is to develop a technique suitable for characterizing both the negative BTI (NBTI) and positive BTI (PBTI) in SRAM. The key issues addressed include the SRAM relevant sensing Vg, measurement delay, capturing the upper envelope of degradation, sampling rate, and measurement time window. The differences between NBTI and PBTI are highlighted. The impact of NBTI and PBTI on the cell-level performance is assessed by simulation, based on experimental results obtained from individual devices. The simulation results show that, for a given static noise margin, test conditions have a significant effect on the minimum operation bias

Energy Distribution of Positive Charges in Al2O3/GeO2/Ge pMOSFETs

The high hole mobility of Ge makes it a strong candidate for end of roadmap pMOSFETs and low interface states have been achieved for the Al2O3-GeO2-Ge gate-stack. This structure, however, suffers from significant negative bias temperature instability (NBTI), dominated by positive charge (PC) in Al2O3/GeO2. An in-depth understanding of the PCs will assist in the minimization of NBTI and the defect energy distribution will provide valuable information. The energy distribution also provides the effective charge density at a given surface potential, a key parameter required for simulating the impact of NBTI on device and circuit performance. For the first time, this letter reports the energy distribution of the PC in Al2O3/GeO2 on Ge. It is found that the energy density of the PC has a clear peak near Ge Ec at the interface and a relatively low level between Ec and Ev. Below Ev at the interface, it increases rapidly and screens 20% of the Vg rise