A high efficiency BPSK receiver for short range wireless network

In this paper, a 910MHz high efficiency BPSK receiver is presented with Colpitts oscillator for short range wireless network. In this research, with injection-lock technique and using Colpitts oscillator, the efficiency of receiver has been improved. And also, behavior of an oscillator under injection of another signal has been investigated. Also, variation of output signal amplitude versus injected signal phase variation, the effect of varying the amplitude of injected signal and quality factor of the oscillator has been investigated. The designed receiver has 0.474 mW dc power and -60 dBm sensitivity. Data rate of receiver is 5 Mbps. The FOM of receiver is 94 pJ/bit. This receiver was designed and simulated in 0.18 μm RFCMOS technology. This proposed receiver can be used in short range wireless network for example, Wireless Body array network and wireless sensor network

Persian/Arabic document Segmentation Based on Pyramidal Image Structure

Automatic transformation of paper documents into electronic documents requires document segmentation at the first stage. However, some parameters restrictions such as variations in character font sizes, different text line spacing, and also not uniform document layout structures altogether have made it difficult to design a general-purpose document layout analysis algorithm for many years. Thus in most previously reported methods it is inevitable to include these parameters. This problem becomes excessively acute and severe, especially in Persian/Arabic documents. Since the Persian/Arabic scripts differ considerably from the English scripts, most of the proposed methods for the English scripts do not render good results for the Persian scripts. In this paper, we present a novel parameter-free method for segmenting the Persian/Arabic document images which also works well for English scripts. This method segments the document image into maximal homogeneous regions and identifies them as texts and non-texts based on a pyramidal image structure. In other words the proposed method is capable of document segmentation without considering the character font sizes, text line spacing, and document layout structures. This algorithm is examined for 150 Arabic/Persian and English documents and document segmentation process are done successfully for 96 percent of documents

Persian/Arabic document Segmentation Based on Pyramidal Image Structure

Automatic transformation of paper documents into electronic documents requires document segmentation at the first stage. However, some parameters restrictions such as variations in character font sizes, different text line spacing, and also not uniform document layout structures altogether have made it difficult to design a general-purpose document layout analysis algorithm for many years. Thus in most previously reported methods it is inevitable to include these parameters. This problem becomes excessively acute and severe, especially in Persian/Arabic documents. Since the Persian/Arabic scripts differ considerably from the English scripts, most of the proposed methods for the English scripts do not render good results for the Persian scripts. In this paper, we present a novel parameter-free method for segmenting the Persian/Arabic document images which also works well for English scripts. This method segments the document image into maximal homogeneous regions and identifies them as texts and non-texts based on a pyramidal image structure. In other words the proposed method is capable of document segmentation without considering the character font sizes, text line spacing, and document layout structures. This algorithm is examined for 150 Arabic/Persian and English documents and document segmentation process are done successfully for 96 percent of documents

Persian/Arabic document Segmentation Based on Pyramidal Image Structure

Automatic transformation of paper documents into electronic documents requires document segmentation at the first stage. However, some parameters restrictions such as variations in character font sizes, different text line spacing, and also not uniform document layout structures altogether have made it difficult to design a general-purpose document layout analysis algorithm for many years. Thus in most previously reported methods it is inevitable to include these parameters. This problem becomes excessively acute and severe, especially in Persian/Arabic documents. Since the Persian/Arabic scripts differ considerably from the English scripts, most of the proposed methods for the English scripts do not render good results for the Persian scripts. In this paper, we present a novel parameter-free method for segmenting the Persian/Arabic document images which also works well for English scripts. This method segments the document image into maximal homogeneous regions and identifies them as texts and non-texts based on a pyramidal image structure. In other words the proposed method is capable of document segmentation without considering the character font sizes, text line spacing, and document layout structures. This algorithm is examined for 150 Arabic/Persian and English documents and document segmentation process are done successfully for 96 percent of documents

DESIGN AND SIMULATION OF HIGH PRECISION SECOND-ORDER SIGMA-DELTA MODULATOR FOR BLUETOOTH APPLICATIONS

A second-order sigma-delta modulator is presented in this paper which, according to the considered standards, is suitable for bluetooth applications. The oversampling ratio and signal bandwidth of the proposed modulator is 128 and 1 MHz, respectively. The Signal to Noise and Distortion Ratio (SNDR) of the proposed structure is achieved 74 dB, equivalent to 12-bit accuracy, which is desirable precision for the aforementioned application. Utilizing highperformance blocks to implement the system at the circuit level, the sigma-delta modulator has obtained an overall desirable performance more specifically in terms of minimizing the power consumption. The modulator is simulated in 180 nm CMOS TSMC technology at cadence software applying 1.8 V supply voltage. The power consumption is obtained as low as 1.9 mW very suitable for portable modern ultra-low power applications

A Low Voltage Recycling Folded Cascode OTA based on novel CMRR Magnifier

In this paper, a new recycling folded Cascode Operational Trans-conductance Amplifier (OTA) based on a novel Common Mode Rejection Ratio (CMRR) magnifier block is presented. Further, the principle of its operation is discussed in comparison with the conventional recycling folded Cascode OTA. The supply voltage is decreased in the proposed CMRR Magnifier based Recycling Folded Cascode (CMRFC) OTA, due to the elimination of the Cascode transistors. The common mode current is significantly removed by the CMRR magnifier block, which subsequently yields to a relatively higher CMRR compared with its conventional version. The DC bias voltage of the Cascode stage is also eliminated, incorporating the self Cascode structure. To provide a fair comparison, the CMRFC OTA is simulated along with its conventional version, namely the Double Recycling Folded Cascode (DRFC) OTA structure, at Cadence environment by considering the 180nm CMOS technology. The simulation results for the proposed OTA yield 53.4 dB DC-gain, 80.32 degree phase margin and 86.87 dB CMRR with 1.5 volt supply voltage, making it a suitable choice for low-voltage applications

Design and Simulation of an Efficient Quaternary Full-Adder Based on Carbon Nanotube Field Effect Transistor

The essential reason for implementing multilevel processing systems is to reduce the number of semiconductor elements and hence the complexity of system. Multilevel processing systems are realized much easier by carbon nanotube field effect transistors (CNTFET) than MOSFET transistors due to the CNTFET transistors' adjustable threshold voltage capabilities. In this paper, an efficient quaternary full-adder based on CNTFET technology is presented which consists of two half adder blocks, a quaternary decoder and a carry generator circuit. In the proposed architecture, the base-two and base-four circuit design techniques are combined to take the full advantages of both techniques namely simple implementation and low chip area occupation of the entire proposed quaternary full-adder. The proposed structure is evaluated using the Stanford 32nm CNTFET library in HSPICE software. The simulation results for the proposed full-adder structure utilizing a supply voltage of 0.9 volts, reveals the power consumption, propagation delay and energy index equal to 2.67 μW, 40 ps, and 10.68 aJ, respectively

Design and Simulation of Second Order Sigma-Delta Modulator with Very High Precision and Low Power Consumption for Medical Applications

In this paper, a second order sigma delta modulator is presented that is suitable for medical applications. Using the amplifier and comparator circuits with low power consumption, which are utilized in integrator and comparator, respectively, the power consumption of this modulator has significantly decreased; as one of essential requirements for medical devices. SNDR of the proposed modulator is obtained 102.44 dB which is equal to 16.72 bit implying a high accurate structure. System level analysis and circuit level simulation of the modulator are performed at Matlab and Cadence software, respectively. 180nm CMOS technology is utilized for simulation of the circuit. Comparing the proposed Sigma-Delta modulator with similar works reveals the superior performance of this proposed architecture considering the power consumption and accuracy. In order to accomplish a comprehensive comparison and achieve an overall insight into the performance of the circuit a figure of merit (FOM) is presented including modulator's total power consumption, effective number of bits and bandwidth