Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest

MEC bajo TIN2013-42253-PThis paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the rounding logic of arithmetic units, including sticky-bit computation. This is shown for floating-point adders, multipliers, and converters. Experimental analysis demonstrates that HUB formats and the corresponding arithmetic units maintain the same accuracy as conventional ones. On the other hand, the implementation of these units, based on basic architectures, shows that HUB formats simultaneously improve area, speed, and power consumption. Specifically, based on data obtained from the synthesis, a HUB single-precision adder is about 14% faster but consumes 38% less area and 26% less power than the conventional adder. Similarly, a HUB single-precision multiplier is 17% faster, uses 22% less area, and consumes slightly less power than conventional multiplier. At the same speed, the adder and multiplier achieve area and power reductions of up to 50% and 40%, respectively

New formats for computing with real-numbers under round-to-nearest

An edited version of this work was accepted in IEEE Transactions on computers, DOI 10.1109/TC.2015.2479623In this paper, a new family of formats to deal with real number for applications requiring round to nearest is proposed. They are based on shifting the set of exactly represented numbers which are used in conventional radix-R number systems. This technique allows performing radix complement and round to nearest without carry propagation with negligible time and hardware cost. Furthermore, the proposed formats have the same storage cost and precision as standard ones. Since conversion to conventional formats simply require appending one extra-digit to the operands, standard circuits may be used to perform arithmetic operations with operands under the new format. We also extend the features of the RN-representation system and carry out a thorough comparison between both representation systems. We conclude that the proposed representation system is generally more adequate to implement systems for computation with real number under round-to-nearest.Ministry of Education and Science of Spain under contracts TIN2013-42253-P

Floating Point Square Root under HUB Format

Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is required because it is performed simply by truncation. From a hardware point of view, the circuits implementing this representation save both area and time since rounding does not involve any carry propagation. Designs to perform the four basic operations have been proposed under HUB format recently. Nevertheless, the square root operation has not been confronted yet. In this paper we present an architecture to carry out the square root operation under HUB format for floating point numbers. The results of this work keep supporting the fact that the HUB representation involves simpler hardware than its conventional counterpart for computers requiring round-to-nearest mode.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tec

Simplified Floating-Point Units for High Dynamic Range Image and Video Systems

The upcoming arrival of high dynamic range image and video applications to consumer electronics will force the utilization of floating-point numbers on them. This paper shows that introducing a slight modification on classical floating-point number systems, the implementation of those circuits can be highly improved. For a 16-bit numbers, by using the proposed format, the area and power consumption of a floating-point adder is reduced up to 70% whereas those parameters are maintained for the case of a multiplier.This work was supported in part by the Ministry of Education and Science of Spain and Junta of Andalucía under contracts TIN2013-42253-P and TIC-1692, respectively, and Universidad de Málaga.Campus de Excelencia Internacional Andalucía Tech

Unbiased Rounding for HUB Floating-point Addition

Copyright (c) 2018 IEEE doi:10.1109/TC.2018.2807429Half-Unit-Biased (HUB) is an emerging format based on shifting the represented numbers by half Unit in the Last Place. This format simplifies two’s complement and roundto- nearest operations by preventing any carry propagation. This saves power consumption, time and area. Taking into account that the IEEE floating-point standard uses an unbiased rounding as the default mode, this feature is also desirable for HUB approaches. In this paper, we study the unbiased rounding for HUB floating-point addition in both as standalone operation and within FMA. We show two different alternatives to eliminate the bias when rounding the sum results, either partially or totally. We also present an error analysis and the implementation results of the proposed architectures to help the designers to decide what their best option are.TIN2013-42253-P, TIN2016-80920-R, JA2012P12-TIC-169

A Proposal for Compensation between TSOs for Cross Border Trades

The increasing amount of power exchanges in the European networks makes necessary to design a method for the allocation of the grid costs incurred by these exchanges. This paper presents a method that complies with the conditions required by the regulatory authorities and is technically sound. It calculates the compensation due to a grid using a differential method, while the contributions of the grid users are calculated by the Simplified Average Participation approachX Portuguese-Spanish Conference in Electrical EngineeringNo publicad

Fast HUB Floating-point Adder for FPGA

Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point adder for FPGA which greatly improves the speed of previous proposed HUB designs for these devices. Our architecture is based on the double path technique which reduces the execution time since each path works in parallel. We also deal with the implementation of unbiased rounding in the proposed adder. Experimental results are presented showing the goodness of the new HUB adder for FPGA.TIN2016- 80920-R, JA2012 P12-TIC-1692, JA2012 P12-TIC-147

Reproducible SUmmation under HUB Format

Version diferente del paper presentado en el congresoFloating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any carry propagation and saving time and area. In this paper we study the reproducible summation of HUB numbers by using a errorfree vector transformation technique, providing both a specific architecture and the usage of combined HUB/Standard floating point adders to achieve a reproducible resultUniversidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Los palacios calcinados.

Réflexions sur la complexe identité mexicaine à partir des oeuvres d’Octavio Paz et Carlos Fuentes