Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors

We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-k dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 us, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple DC characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/um. In addition, using modeling and capacitance-voltage measurements we extract charge trap densities up to 10^12 1/cm^2 in the top gate dielectric (here Al2O3). Our study illustrates important time- and field-dependent imperfections of top-gated GFETs with high-k dielectrics, which must be carefully considered for future developments of this technologyComment: to appear in IEEE Transactions on Electron Devices (2014

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture has been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 26.67 % improvement in speed, 5.966 % improvement in power consumption and 31.06 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors

Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors

Abstract-We measure top-gated graphene field-effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-κ dielectric or graphene imperfections, the drain current decreases by ∼10% over timescales of ∼10 μs, consistent with charge trapping mechanisms. The pulsed operation leads to hysteresis-free I-V characteristics that are studied with pulses as short as 75 and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple dc characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/μm. In addition, using modeling and capacitance-voltage measurements, we extract trap densities up to 10 12 cm −2 in the top-gate dielectric (here Al 2 O 3 ). This study illustrates important time-and field-dependent imperfections of top-gated GFETs with high-κ dielectrics, which must be carefully considered for future developments of this technology

ATOMISTIC MODELING OF UNINTENTIONAL SINGLE CHARGE EFFECTS IN NANOSCALE FETS

Numerical simulations have been performed to study the single-charge-induced ON current fluctuations (random telegraphic noise) in conventional (MOSFET) and non-conventional (silicon nanowire) nanoscale field-effect transistors. A semi-classical three-dimensional particle-based Monte Carlo device simulator (MCDS 3-D) has been integrated and used in this work. Quantum mechanical space-quantization effects have been accounted for via a parameter-free effective potential scheme that has been proved quite successful in describing charge set back from the interface and quantization of the energy (bandgap widening) within the channel region of the device. The effective potential is based on a perturbation theory around thermodynamic equilibrium and leads to a quantum field formalism in which the size of the electron depends upon its energy. To treat full Coulomb (electron-ion and electron-electron) interactions properly, the simulator implements two different real-space molecular dynamics (MD) schemes: the particle-particle-particle-mesh (P3M) method and the corrected Coulomb approach. For better accuracy, particularly in case of nanowire FETs, bandstructure parameters (bandgap, effective masses, and density of states) have been computed via a 20-band nearest-neighbor sp3d5s* tight-binding scheme. Also, since the presence of single impurities in the channel region represents a rare event in the carrier transport process, necessary event-biasing algorithms have been implemented in the simulator that, while enhancing the statistics, results in a faster convergence in the chan-nel current. The study confirms that, due to the presence of single channel charges, both the electrostatics (carrier density) and dynamics (mobility) are modified and, therefore, simultaneously play important roles in determining the magnitude of the current fluctuations. The relative impact (percentage change in the ON current) depends on an intricate interplay of device size, geometry, crystal direction, gate bias, temperature, and energetics and spatial location of the trap

Substrate-dependent high-field transport and self-heating in graphene transistors

Over the last decade graphene has attracted much interest for nanoelectronic applications due to its high and symmetrical carrier mobility, and high drift velocity compared to silicon. However, when graphene is placed on insulating substrates such as SiO2 or flexible plastics, its inherent superior qualities get suppressed by the influence of the underlying substrate. Interfaces and substrate material properties have a significant impact on graphene based nano-scale devices due to the reduced dimensions and large surface-to-volume ratio. Motivated by this issue, in this work we have investigated the substrate dependence of the electrical and thermal transport in graphene field-effect transistors (GFETs). We developed a simple yet practical electro-thermal model along with extensive calibration with experimental data. Special emphasis is given to the study of high-field transport and investigation of temperature-induced effects on device performance. First, we have used this electro-thermal model to examine the scaling effect of the supporting insulator (e.g. SiO2, BN) thickness on temperature maximum (hot spot) formation. Our findings showed average and maximum temperatures of GFETs scale differently due to competing electrostatic and heat sinking effects. Self-heating in GFETs causes current degradation (up to ~10-20%) in micron-sized devices on SiO2/Si but is reduced if the supporting insulator thickness is scaled down. The transient behavior of such FETs has thermal time constants in the range of 50-250 ns, dominated by the thickness of the supporting insulator and that of device capping layers. Self-heating is also reduced in shorter channel devices, due to partial heat sinking at the contacts. Next, we investigate the effect of different supporting dielectrics such as hexagonal boron nitride (h-BN), HfO2 and SiO2 on the velocity saturation of GFETs. We examine the effects from different substrates as they each present a unique scenario due to their different (re-mote) phonons and thermal conductivities, all of which influence high-field transport in GFETs. Additionally, we studied the origins of the poor current saturation in short-channel GFETs in de-tail. We study and compare the temperature profiles generated in GFETs on different insulating materials for bottom oxide and substrate through full thermal finite element method (FEM). Ma-terials with anisotropic thermal conductivity showed significant impact in heat spreading and temperature rise in the hot-spot. We apply our findings to add a guideline for the maximum “safe” power density, e.g. in GFETs on flexible substrates such as polyimide (PI), without inducing thermal deformation; the maximum is found to be ~1.8 mW/µm2 (with 200 nm BN dielectric). Finally, we also develop a physics-based compact model based on existing literature, for GFETs with well calibration against experimental data and other finite element models. This model has been implemented into a circuit simulator like Verilog-A with a minimum number of iterations for channel potential calculation. These results shed important physical insight into the high-field and thermal profile of graphene transistors. Moreover, the electro-thermal model and results presented in this dissertation can be extended for analysis of other 2D materials beyond graphene

Smart Home System: A Comprehensive Review

Smart home is a habitation that has been outfitted with technological solutions that are intended to provide people with services that are suited to their needs. The purpose of this article is to perform a systematic assessment of the latest smart home literature and to conduct a survey of research and development conducted in this field. In addition to presenting a complete picture of the current smart home system’s (SHS) development and characteristics, this paper provides a deep insight into latest hardware and trends. The research then moves on to a detailed discussion of some of the important services provided by the SHS and its advantages. The paper also statistically discusses the current and future research trends in the SHS, followed by a detailed portrayal of the difficulties and roadblocks in implementing them. The comprehensive overview of the SHS presented in this paper will help designers, researchers, funding agencies, and policymakers have a bird’s-eye view of the overall concept, attributes, technological aspects, and features of modern SHSs