Ratioless full-complementary 12-transistor static random access memory for ultra low supply voltage operation

In this study, a ratioless full-complementary 12-transistor static random access memory (SRAM) was developed and measured to evaluate its operation under an ultra low supply voltage range. The ratioless SRAM design concept enables a memory cell design that is free from the consideration of the static noise margin (SNM). Furthermore, it enables a SRAM function without the restriction of transistor parameter (W/L) settings and the dependence on the variability of device characteristics. The test chips that include both conventional 6-transistor SRAM cells and the ratioless full-complementary 12-transistor SRAM cells were developed by a 180 nm CMOS process to compare their stable operations under an ultralow supply voltage condition. The measured results show that the ratioless full-complementary 12-transistor SRAM has superior immunity to device variability, and its inherent operating ability at the supply voltage of 0.22 V was experimentally confirmed

A Measurement of Ratio-less 12-transistor SRAM cell Operation at Ultra-low Supply-voltage

2014 International Conference on Solid State Devices and Materials (SSDM 2014), September 8-11, 2014, Tsukuba, Ibaraki, Japa

Vth-Shiftable SRAM Cell TEGs for Direct Measurement for the immunity of the Threshold Voltage Variability

We developed VTSTs for 6T-SRAM and RL-SRAM and evaluated them to investigate the influences of SRAM operation by Vth fluctuation using measured FCMs and CΔVths. As a result, we successfully confirmed the superior immunity of Vth fluctuation of the RL-SRAM than the 6T-SRAM.IEEE International Conference on Microelectronic Test Structures (ICMTS 2017), 27-30 March 2017, Grenoble, Franc

Monte Carlo Analysis by Direct Measurement using Vth-shiftable SRAM Cell TEG

The measurement system in which the Monte Carlo analysis of SRAM operation can be performed in actual measurement using Vth-shiftable SRAM cell TEG (VTST) was developed. The dynamic Vth-shift circuit (DVSC) using electrolytic capacitors and mechanical relays for setting individual Vth-shift voltages for six MOSFETs in a memory cell enables to share a programmable external voltage source. The measured results of the Monte Carlo analysis for SRAM function test and the static noise margin evaluation were agreed well with the simulated results. The proposed method can compactly cope with the recently proposed SRAM with a larger number of transistors.IEEE International Conference on Microelectronic Test Structures (ICMTS 2018), 19-22 March 2018, Austin, TX, US

A Vth-Shiftable SRAM Cell TEGs for Direct Measurement for the immunity of the Threshold Voltage Variability

IEEE/ACM Workshop on Variability Modeling and Characterization (VMC 2016), November 10, 2016, Austin, TX, US

A Measurement of Ratio-less 12-transistor SRAM cell Operation at Ultra-low Supply-voltage

2014 International Conference on Solid State Devices and Materials (SSDM 2014), September 8-11, 2014, Tsukuba, Ibaraki, Japa

Ratioless full-complementary 12-transistor static random access memory for ultra low supply voltage operation

In this study, a ratioless full-complementary 12-transistor static random access memory (SRAM) was developed and measured to evaluate its operation under an ultra low supply voltage range. The ratioless SRAM design concept enables a memory cell design that is free from the consideration of the static noise margin (SNM). Furthermore, it enables a SRAM function without the restriction of transistor parameter (W/L) settings and the dependence on the variability of device characteristics. The test chips that include both conventional 6-transistor SRAM cells and the ratioless full-complementary 12-transistor SRAM cells were developed by a 180 nm CMOS process to compare their stable operations under an ultralow supply voltage condition. The measured results show that the ratioless full-complementary 12-transistor SRAM has superior immunity to device variability, and its inherent operating ability at the supply voltage of 0.22 V was experimentally confirmed

A Vth-Shiftable SRAM Cell TEGs for Direct Measurement for the immunity of the Threshold Voltage Variability

IEEE/ACM Workshop on Variability Modeling and Characterization (VMC 2016), November 10, 2016, Austin, TX, US

Monte Carlo Analysis by Direct Measurement using Vth-shiftable SRAM Cell TEG

The measurement system in which the Monte Carlo analysis of SRAM operation can be performed in actual measurement using Vth-shiftable SRAM cell TEG (VTST) was developed. The dynamic Vth-shift circuit (DVSC) using electrolytic capacitors and mechanical relays for setting individual Vth-shift voltages for six MOSFETs in a memory cell enables to share a programmable external voltage source. The measured results of the Monte Carlo analysis for SRAM function test and the static noise margin evaluation were agreed well with the simulated results. The proposed method can compactly cope with the recently proposed SRAM with a larger number of transistors.IEEE International Conference on Microelectronic Test Structures (ICMTS 2018), 19-22 March 2018, Austin, TX, US

Vth-shiftable SRAM cell TEGs for direct measurement for the immunity of the threshold voltage variability

We developed VTSTs for 6T-SRAM and RL-SRAM and evaluated them to investigate the influences of SRAM operation by Vth fluctuation using measured FCMs and CΔVths. As a result, we successfully confirmed the superior immunity of Vth fluctuation of the RL-SRAM than the 6T-SRAM.IEEE International Conference on Microelectronic Test Structures (ICMTS 2017), 27-30 March 2017, Grenoble, Franc