Selective rendering for efficient ray traced stereoscopic images

Depth-related visual effects are a key feature of many virtual environments. In stereo-based systems, the depth effect can be produced by delivering frames of disparate image pairs, while in monocular environments, the viewer has to extract this depth information from a single image by examining details such as perspective and shadows. This paper investigates via a number of psychophysical experiments, whether we can reduce computational effort and still achieve perceptually high-quality rendering for stereo imagery. We examined selectively rendering the image pairs by exploiting the fusing capability and depth perception underlying human stereo vision. In ray-tracing-based global illumination systems, a higher image resolution introduces more computation to the rendering process since many more rays need to be traced. We first investigated whether we could utilise the human binocular fusing ability and significantly reduce the resolution of one of the image pairs and yet retain a high perceptual quality under stereo viewing condition. Secondly, we evaluated subjects' performance on a specific visual task that required accurate depth perception. We found that subjects required far fewer rendered depth cues in the stereo viewing environment to perform the task well. Avoiding rendering these detailed cues saved significant computational time. In fact it was possible to achieve a better task performance in the stereo viewing condition at a combined rendering time for the image pairs less than that required for the single monocular image. The outcome of this study suggests that we can produce more efficient stereo images for depth-related visual tasks by selective rendering and exploiting inherent features of human stereo vision

A new robust handshake for asymmetric asynchronous micro-pipelines

[[abstract]]In this paper, a new handshake methodology to enhance the performance of the asynchronous micro-pipeline systems is proposed. The proposed handshake methodology has more flexibilities to design an asymmetric asynchronous micro-pipeline system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. Others, the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. An asynchronous micro-pipeline array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35μm CMOS technology, the simulation results show that the proposed new handshake methodology has shortest latency and more robust property as compare with other handshake methodologies.[[conferencetype]]國際[[conferencedate]]20030525~20030528[[booktype]]紙本[[conferencelocation]]Bangkok, Thailan

Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization

[[abstract]]Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: "does any rule exist that contains all good?" This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and is suitable for low supply voltage. It has full swing signal in all nodes and high robustness against transistor downsizing and voltage scaling[[notice]]補正完畢[[conferencetype]]國際[[conferencedate]]20020107~20020107[[conferencelocation]]Bangalore, Kannad

OE-6 Building a Personal Brand on Social Media from Experiential Marketing Perspective - A Case Study on Indonesia’s Fashion Instagrammers

Instagram enhances online presence and identity, and allows more effective interaction not only for personal reasons, but also for business purposes. Experiential marketing is a new marketing concept that focusing on creative and innovative ways to appeal customers' senses, feelings, intellect, curiousity and self image rather than to rational, utilitarian notions of value. This paper aims to study about how the certain personality could build up their personal brand with Instagram as their main media from the experiential marketing view with the Analytical Hierarchy Process. Instagram fashion personal brands in Indonesia were the main source of the data collection. By the research, Sense factor is the most important strategic experiential module factor as in its relation with notable visual strength of Instagram. To be able to apply the Sense as a strategic experiential module, the consideration about tactical and practical factors are required. The 5 most important tactical factor is the Visual Elements factor, in which is about producing vivid content, Personality, a factor in terms of showing one true self, Relationship factor related to things about managing and maintaining relationships between stakeholders on Instagram environment, Signature, the factor about showing their own brand DNA, and Verbal Elements, the factor about communication in form of words. For practical factors are Image, by the image processing results and image taking directions, Apparel, with clothing combinations, style and brands, Authenticity, by being one true self, Caption, with the wording on every posts, and Brand and Followers, as brand to create a link or connection. As the implications, the fashion personal brands as the influencers could apply the key to draw attention from the audiences and make an impact to fashion enterprises in Indonesia

The suggestion for CFS CMOS buffer

[[abstract]]Two recent papers, one by Huang et al. (1996) and the other by Cheng et al. (1997), on the driver buffer are commented on. The feedback-controlled split-path CMOS buffer (FS) claims that the 4-split-path buffer can reduce the power and power-delay product. But the voltage of the gates in the output inverter stage is not enough to turn-off the PMOS transistor and the NMOS transistor. Due to this, charge-recovery must be used. The charge-transfer feedback-controlled split-path (CFS) CMOS buffer that has high-speed low-power performance by using transfer of the charge stored in the split output-stage driver to the output node. Thus the power-delay product can be reduced greatly by combining the technology described in the former two papers. The HSPICE simulation results show that the power-delay product of the suggested CMOS buffer is reduced by 20% to 40% in comparison to the conventional CMOS tapered buffer at 100 MHz operation frequency at heavy capacitive load[[conferencetype]]國際[[conferencedate]]19990905~19990908[[booktype]]紙本[[conferencelocation]]Pafos, Cypru

Design of current mode operational amplifier with differential-input and differential-output

[[abstract]]In this paper, a CMOS implementation of a current operational amplifier (COA) with a differential input and a differential output is described. The amplifier is configured from a differential current mirror input transimpedance stage followed by a differential output transconductance gain stage. A differential mode design technique is proposed and used in the feedback circuit. This configuration is the current mode counterpart of the traditional voltage mode operational amplifier (VOA). In this design, the simulation results exhibit an open-loop differential gain of 51.71 dB with the gain-bandwidth product 314 MHz and a settling time of 14 ns.[[conferencetype]]國際[[conferencedate]]19970609~19970612[[iscallforpapers]]Y[[conferencelocation]]Hong Kon

Role of SiNx Barrier Layer on the Performances of Polyimide Ga2O3-doped ZnO p-i-n Hydrogenated Amorphous Silicon Thin Film Solar Cells

In this study, silicon nitride (SiNx) thin films were deposited on polyimide (PI) substrates as barrier layers by a plasma enhanced chemical vapor deposition (PECVD) system. The gallium-doped zinc oxide (GZO) thin films were deposited on PI and SiNx/PI substrates at room temperature (RT), 100 and 200 °C by radio frequency (RF) magnetron sputtering. The thicknesses of the GZO and SiNx thin films were controlled at around 160 ± 12 nm and 150 ± 10 nm, respectively. The optimal deposition parameters for the SiNx thin films were a working pressure of 800 × 10−3 Torr, a deposition power of 20 W, a deposition temperature of 200 °C, and gas flowing rates of SiH4 = 20 sccm and NH3 = 210 sccm, respectively. For the GZO/PI and GZO-SiNx/PI structures we had found that the GZO thin films deposited at 100 and 200 °C had higher crystallinity, higher electron mobility, larger carrier concentration, smaller resistivity, and higher optical transmittance ratio. For that, the GZO thin films deposited at 100 and 200 °C on PI and SiNx/PI substrates with thickness of ~1000 nm were used to fabricate p-i-n hydrogenated amorphous silicon (α-Si) thin film solar cells. 0.5% HCl solution was used to etch the surfaces of the GZO/PI and GZO-SiNx/PI substrates. Finally, PECVD system was used to deposit α-Si thin film onto the etched surfaces of the GZO/PI and GZO-SiNx/PI substrates to fabricate α-Si thin film solar cells, and the solar cells’ properties were also investigated. We had found that substrates to get the optimally solar cells’ efficiency were 200 °C-deposited GZO-SiNx/PI

The non-full voltage swing TSPC (NSTSPC) logic design

[[abstract]]In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 μm CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage[[abstract]]In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 μm CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage.[[conferencetype]]國際[[conferencedate]]20000828~20000830[[booktype]]紙本[[conferencelocation]]Cheju, Kore