Between Sinology and Socialism: Collective Memory of Czech Sinologists in the 1950s

This paper intends to explore the collective memory of Czech sinologists in the 1950s based on the political zone between sinology and socialism. Czech sinological development in the 1950s was grounded on the personal factor of Prusek and the socialist transformation of new China. Socialist China offers two possibilities for the development of sinology, the first for friendly relations among socialist countries, including overseas students, and the second for studies of contemporary Chinese literature. The developmental framework of Czech sinology in the 1950s, or the social framework of collective memory for the Czech sinologists should be understood in the region under the mutual penetration of sinology and socialist China. This paper, firstly, discusses the background framework of constructing the Czech sinologists in the 1950s— the link between new China and the other socialist countries, and the relation between Prusek and socialist China. Secondly, this paper will analyze Czech sinological experiences in the 1950s through Halbwachs’ theory of collective memory.Mongolian Journal of International Affairs Vol.19 2014: 116-13

The Impact of Breakdowns on the Decision to Consolidate or Cluster Computers

More and more organizations are running a clustered twin-computer system to tackle the rapidly growing demand of computer capacity. A prevailing rationale for a clustered twin-computer system isthat it is an effective way of coping with not only the capacity growth challenge but also the computer downtime problem. This paper develops an analytical model for a clustered twin-computer system subject to breakdowns with an aim to identifying conditions under which the clustered twin-computer system is a better alternative to a consolidated system. This research finds that the clustered twin-computer system has a shorter expected time in system for most cases. The clustered twin-computer system also performs better when there is a heavy traffic intensity. For firms with a consolidated single computer system, this research finds that it pays off to reduce the mean time to repair than to increase the mean time between failure

Selective rendering for efficient ray traced stereoscopic images

Depth-related visual effects are a key feature of many virtual environments. In stereo-based systems, the depth effect can be produced by delivering frames of disparate image pairs, while in monocular environments, the viewer has to extract this depth information from a single image by examining details such as perspective and shadows. This paper investigates via a number of psychophysical experiments, whether we can reduce computational effort and still achieve perceptually high-quality rendering for stereo imagery. We examined selectively rendering the image pairs by exploiting the fusing capability and depth perception underlying human stereo vision. In ray-tracing-based global illumination systems, a higher image resolution introduces more computation to the rendering process since many more rays need to be traced. We first investigated whether we could utilise the human binocular fusing ability and significantly reduce the resolution of one of the image pairs and yet retain a high perceptual quality under stereo viewing condition. Secondly, we evaluated subjects' performance on a specific visual task that required accurate depth perception. We found that subjects required far fewer rendered depth cues in the stereo viewing environment to perform the task well. Avoiding rendering these detailed cues saved significant computational time. In fact it was possible to achieve a better task performance in the stereo viewing condition at a combined rendering time for the image pairs less than that required for the single monocular image. The outcome of this study suggests that we can produce more efficient stereo images for depth-related visual tasks by selective rendering and exploiting inherent features of human stereo vision

A new robust handshake for asymmetric asynchronous micro-pipelines

[[abstract]]In this paper, a new handshake methodology to enhance the performance of the asynchronous micro-pipeline systems is proposed. The proposed handshake methodology has more flexibilities to design an asymmetric asynchronous micro-pipeline system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. Others, the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. An asynchronous micro-pipeline array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35μm CMOS technology, the simulation results show that the proposed new handshake methodology has shortest latency and more robust property as compare with other handshake methodologies.[[conferencetype]]國際[[conferencedate]]20030525~20030528[[booktype]]紙本[[conferencelocation]]Bangkok, Thailan

Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization

[[abstract]]Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: "does any rule exist that contains all good?" This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and is suitable for low supply voltage. It has full swing signal in all nodes and high robustness against transistor downsizing and voltage scaling[[notice]]補正完畢[[conferencetype]]國際[[conferencedate]]20020107~20020107[[conferencelocation]]Bangalore, Kannad