Impact of gate tunnelling leakage on CMOS circuits with full open defects

Electronics Letter of the MonthInterconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.Peer ReviewedAward-winningPostprint (published version

An assessment of polymer nano-composite materials

Includes bibliographical referencesAvailable from British Library Document Supply Centre- DSC:6180. 5139(123) / BLDSC - British Library Document Supply CentreSIGLEGBUnited Kingdo

Impact of gate tunnelling leakage on CMOS circuits with full open defects

Electronics Letter of the MonthInterconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.Peer ReviewedAward-winnin

Relationship of acoustic emission with crack growth in cyclic and static loading

18.00; Translated from Russian (Diagnosika i Prognozirovanie Razrusheniya Svarnykh Konstruktsii 1987 (5) p. 53-56)Available from British Library Document Supply Centre- DSC:9023.19(VR-Trans--3951)T / BLDSC - British Library Document Supply CentreSIGLEGBUnited Kingdo

Diagnosis of full open defects in interconnecting lines

Best Paper Award al millor article del congrés IEEE VLSI Test Symposium 2007A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.Award-winnin

Diagnosis of full open defects in interconnecting lines

Best Paper Award al millor article del congrés IEEE VLSI Test Symposium 2007A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.Award-winnin