Observation of dynamic V-TH of p-GaN Gate HEMTs by fast sweeping characterization

In this work, fast sweeping characterization with an extremely short relaxation time was used to probe the V-TH instability of p-GaN gate HEMTs. As the I-D-V-G sweeping time deceases from 5 ms to 5 mu s, the V-TH dramatically degenerates from 3.13 V to 1.76 V, meanwhile the hysteresis deteriorates from 22.6mV to 1.37 V. Positive bias temperature instability (PBTI) measurement by fast sweeping shows the V-TH features a very fast shifting process but a slower recovering process. D-mode HEMTs counterpart without Mg contamination demonstrates a negligible V-TH shift and hysteresis, proving the V-TH instability is probably due to the ionization of acceptor-like traps in the p-GaN depletion region. Finally, the V-TH instability is verified by a GaN circuit under switching stress. The V-TH instability under different sweeping speed uncovers the fact that the high V-TH by conventionally slow DC measurements is probably artificial. The DC V-TH should be high enough to avoid HEMT faulty turn-on

An investigation on border traps in III-V MOSFETs with an In0.53Ga0.47As channel

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device timeto-failure projection

Perpendicular magnetic anisotropy of CoFeB\Ta bilayers on ALD HfO2

Perpendicular magnetic anisotropy (PMA) is an essential condition for CoFe thin films used in magnetic random access memories. Until recently, interfacial PMA was mainly known to occur in materials stacks with MgO\CoFe(B) interfaces or using an adjacent crystalline heavy metal film. Here, PMA is reported in a CoFeB\Ta bilayer deposited on amorphous high-kappa dielectric (relative permittivity kappa=20) HfO2, grown by atomic layer deposition (ALD). PMA with interfacial anisotropy energy K-i up to 0.49 mJ/m(2) appears after annealing the stacks between 200 degrees C and 350 degrees C, as shown with vibrating sample magnetometry. Transmission electron microscopy shows that the decrease of PMA starting from 350 degrees C coincides with the onset of interdiffusion in the materials. High-kappa dielectrics are potential enablers for giant voltage control of magnetic anisotropy (VCMA). The absence of VCMA in these experiments is ascribed to a 0.6 nm thick magnetic dead layer between HfO2 and CoFeB. The results show PMA can be easily obtained on ALD high-kappa dielectrics

Growth Mechanism of a Hybrid Structure Consisting of a Graphite Layer on Top of Vertical Carbon Nanotubes

Graphene and carbon nanotubes (CNTs) are both carbon-based materials with remarkable optical and electronic properties which, among others, may find applications as transparent electrodes or as interconnects in microchips, respectively. This work reports on the formation of a hybrid structure composed of a graphitic carbon layer on top of vertical CNT in a single deposition process. The mechanism of deposition is explained according to the thickness of catalyst used and the atypical growth conditions. Key factors dictating the hybrid growth are the film thickness and the time dynamic through which the catalyst film dewets and transforms into nanoparticles. The results support the similarities between chemical vapor deposition processes for graphene, graphite, and CNT

Impact of Individual Charged Gate-Oxide Defects on the Entire I D -V G Characteristic of Nanoscaled FETs

Index Terms-Nanoscale, negative bias temperature instability (NBTI), pMOSFET, reliability, time-dependent variability

Design and simulation of on-chip circuits for parallel characterization of ultrascaled transistors for BTI reliability

A novel on-chip test circuit architecture to perform BTI characterization of single devices using the Measure-Stress- Measure (MSM) method is designed and simulations were performed to confirm that the design is fully functional. Characterization throughput was maximized using pipelining. A ‘place-and-check’ algorithm was developed to generate optimized pipelining of individual device measurements. The novel pipelining methodology was corroborated with real measurements, in accordance with the generated pipelining sequence and proposed circuit architecture. The results are shown to be consistent with the data obtained from conventional measurement methods and an improvement of 82% was achieved in total BTI characterization time of 4096 devices.status: publishe

Reliability of high mobility SiGe channel MOSFETs for future CMOS applications

Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and presented here show the reliability improvement to be process- and architecture-independent and, as such, readily transferable to advanced device architectures as Tri-Gate (finFET) devices. We propose a physical model to understand the intrinsically superior reliability of the MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack. The improved reliability properties here discussed strongly support (Si)Ge technology as a clear frontrunner for future CMOS technology nodes