Multimodal regularised linear models with flux balance analysis for mechanistic integration of omics data

Motivation: High-throughput biological data, thanks to technological advances, have become cheaper to collect, leading to the availability of vast amounts of omic data of different types. In parallel, the in silico reconstruction and modeling of metabolic systems is now acknowledged as a key tool to complement experimental data on a large scale. The integration of these model- and data-driven information is therefore emerging as a new challenge in systems biology, with no clear guidance on how to better take advantage of the inherent multisource and multiomic nature of these data types while preserving mechanistic interpretation. Results: Here, we investigate different regularization techniques for high-dimensional data derived from the integration of gene expression profiles with metabolic flux data, extracted from strain-specific metabolic models, to improve cellular growth rate predictions. To this end, we propose ad-hoc extensions of previous regularization frameworks including group, view-specific and principal component regularization and experimentally compare them using data from 1143 Saccharomyces cerevisiae strains. We observe a divergence between methods in terms of regression accuracy and integration effectiveness based on the type of regularization employed. In multiomic regression tasks, when learning from experimental and model-generated omic data, our results demonstrate the competitiveness and ease of interpretation of multimodal regularized linear models compared to data-hungry methods based on neural networks. Availability and implementation: All data, models and code produced in this work are available on GitHub at https://github.com/Angione-Lab/HybridGroupIPFLasso_pc2Lasso. Supplementary information: Supplementary data are available at Bioinformatics online

A high-resolution TDC-based board for a fully digital trigger and data acquisition system in the NA62 experiment at CERN

A Time to Digital Converter (TDC) based system, to be used for most sub-detectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital Trigger and Data AcQuisition system (TDAQ), in which the TDC Board (TDCB) and a general-purpose motherboard (TEL62) will play a fundamental role. While TDCBs, housing four High Performance Time to Digital Converters (HPTDC), measure hit times from sub-detectors, the motherboard processes and stores them in a buffer, produces trigger primitives from different detectors and extracts only data related to the lowest trigger level decision, once this is taken on the basis of the trigger primitives themselves. The features of the TDCB board developed by the Pisa NA62 group are extensively discussed and performance data is presented in order to show its compliance with the experiment requirements.Comment: 6 pages, 7 figures, presented to IEEE RT 2014 Conference and I want to publish in TN

Results from CHIPIX-FE0, a Small Scale Prototype of a New Generation Pixel Readout ASIC in 65nm CMOS for HL-LHC

CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 μm2. It is fully functional, can work at low thresholds down to 250e− and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex digital chip. CHIPIX65-FE0 has been irradiated up to 600 Mrad and is only marginally affected on analog performance. Further irradiation to 1 Grad will be performed. Bump bonding to silicon sensors is now on going and detailed measurements will be presented. The HL-LHC accelerator will constitute a new frontier for particle physics after year 2024. One major experimental challenge resides in the inner tracking detectors, measuring particle position: here the dimension of the sensitive area (pixel) has to be scaled down with respect to LHC detectors. This paper describes the results obtained by CHIPIX65-FE0, a readout ASIC in CMOS 65nm designed by the CHIPIX65 project as small-scale demonstrator for a pixel detector at the HL-LHC. It consists of a matrix of 64x64 pixels of dimension 50x50 um2 pixels and contains several pieces that are included in RD53A, a large scale ASIC designed by the RD53 Collaboration: two out of three front-ends (a synchronous and an asynchronous architecture); several building blocks; a (4x4) pixel region digital architecture with central local buffer storage, complying with a 3 GHz/cm2 hit rate and a 1 MHz trigger rate maintaining a very high efficiency (above 99%). The chip is 100% functional, either running in triggered or trigger-less mode. All building-blocks (DAC, ADC, Band Gap, SER, sLVS-TX/RX) and very front ends are working as expected. Analog performance shows a remarkably low ENC of 90e-, a fast-rise time below 25ns and low-power consumption (about 4μA/pixel) in both synchronous and asynchronous front-ends; a very linear behavior of CSA and discriminator. No significant cross talk from digital electronics has been measured, achieving a low threshold of 250e-. Signal digitization is obtained with a 5b-Time over Threshold technique and is shown to be fairly linear, working well either at 80 MHz or with higher frequencies of 300 MHz obtained with a tunable local oscillator. Irradiation results up to 600 Mrad at low temperature (-20°C) show that the chip is still fully functional and analog performance is only marginally degraded. Further irradiation will be performed up to 1 Grad either at low or room temperature, to further understand the level of radiation hardness of CHIPIX65-FE0. We are now in the process of bump bonding CHIPIX65-FE0 to 3D and possibly planar silicon sensors during spring. Detailed results will be presented in the conference paper

A Probe into the Reform of Public Calligraphy Course in Chinese Colleges and Universities

中国书法是中国传统文化中的瑰宝，它既是一门艺术，又有着深厚的文化内涵。我国普通高校开设公共书法教学是与目前倡导的素质教育，培养创新型人才，提倡人的全面和谐发展的高等教育理念相一致的。加强高校公共书法教育，是全面推进素质教育的有效途径之一，也是提高当代大学生人文素质的重要手段。它对促进大学生人格完善、创造力培养以及民族文化的传承等有着不可低估的作用。本文主要针对我国普通高等院校公共书法教学现状进行分析，并由此比较借鉴日本高校中实施书法教学的成功经验提出对我国高校公共书法教学改革的具体建议和措施，设计并实践一种具备学科视野的、以学生为主体的公共书法教学的新模式。论文共分为五部分。引言扼要介绍论文写...Chinese calligraphy is a treasure of Chinese traditional culture. It not only is an art, but also has profound culture contents. Opening the public calligraphy course to the university students is in accordance with the concept that advocated by the current quality- oriented education, which aims to cultivate the students’ creative talent and comprehensive development. This paper concentrates on a...学位：文学硕士院系专业：艺术教育学院美术系_美术学学号：20042201

The DAQPATH readout system of the Serenity boards for the CMS Phase-II Upgrade

The Serenity boards are ATCA custom boards used in the readout of the Phase-II CMS detector. Each board can handle up to 144 optical serial links (up to 25Gb/s each) and supports up to two high-performance FPGAs. In several applications the Serenity board is required to aggregate raw events (FE data) from the detector at every L1 accept and route this event fragment to the central DAQ system. The architecture and behavior of the DAQPATH firmware that collects and merges FE data and manages their transmission to the DAQ system over 25Gb/s output optical links are here described

Design of a radiation-tolerant high-speed driver for Mach Zender Modulators in High Energy Physics

This paper presents the integrated circuit design, targeting a CMOS 65 nm 1.2 V technology, of a high-speed driver that provides the differential input signals to a Mach Zender Modulator (MZM), and allows tuning of the MZM operating point through adjustment of the bias voltage. A multi-voltage domain circuit is proposed, where each domain is isolated through deep n-well trenches, to face the high voltage swing and the bias regulation requirements of the MZM. The MZM device, whose prototype has been implemented in silicon photonics iSiPP50G technology, is emerging as a promising solution for radiation tolerant, several hundreds of Mrad, and high-speed, in the range of 10 Gbps, optical links. These stringent requirements are needed in high energy physics experiments in the upgrade of the Large Hadron Collider or in future Linear Colliders

A simulation framework for the CMS Track Trigger electronics

A simulation framework has been developed to test and characterize algorithms, architectures and hardware implementations of the vastly complex CMS Track Trigger for the high luminosity upgrade of the CMS experiment at the Large Hadron Collider in Geneva. High-level SystemC models of all system components have been developed to simulate a portion of the track trigger. The simulation of the system components together with input data from physics simulations allows evaluating figures of merit, like delays or bandwidths, under realistic conditions. The use of SystemC for high-level modelling allows \mbox{co-simulation} with models developed in Hardware Description Languages, e.g.~VHDL or Verilog. Therefore, the simulation framework can also be used as a test bench for digital modules developed for the final system