Logarithmic behavior of degradation dynamics in metal--oxide semiconductor devices

In this paper the authors describe a theoretical simple statistical modelling of relaxation process in metal-oxide semiconductor devices that governs its degradation. Basically, starting from an initial state where a given number of traps are occupied, the dynamics of the relaxation process is measured calculating the density of occupied traps and its fluctuations (second moment) as function of time. Our theoretical results show a universal logarithmic law for the density of occupied traps $\bar{} \sim \phi (T,E_{F}) (A+B \ln t)$, i.e., the degradation is logarithmic and its amplitude depends on the temperature and Fermi Level of device. Our approach reduces the work to the averages determined by simple binomial sums that are corroborated by our Monte Carlo simulations and by experimental results from literature, which bear in mind enlightening elucidations about the physics of degradation of semiconductor devices of our modern life

Interaction Between Hot Carrier Aging and PBTI Degradation in nMOSFETs: Characterization, Modelling and Lifetime Prediction

Modelling of the interaction between Hot Carrier Aging (HCA) and Positive Bias Temperature Instability (PBTI) has been considered as one of the main challenges in nanoscale CMOS circuit design. Previous works were mainly based on separate HCA and PBTI instead of Interacted HCA-PBTI Degradation (IHPD). The key advance of this work is to develop a methodology that enables accurate modelling of IHPD through understanding the charging/discharging and generation kinetics of different types of defects during the interaction between HCA and PBTI. It is found that degradation during alternating HCA and PBTI stress cannot be modelled by independent HCI/PBTI. Different stress sequence, i.e. HCA-PBTI-HCA and PBTI-HCA-PBTI, lead to completely different degradation kinetics. Based on the Cyclic Anti-neutralization Model (CAM), for the first time, IHPD has been accurately modelled for both short and long channel devices. Complex degradation mechanisms and kinetics can be well explained by our model. Our results show that device lifetime can be underestimated by one decade without considering interaction

Development of a Technique for Characterizing Bias Temperature Instability-Induced Device-to-Device Variation at SRAM-Relevant Conditions

SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse-(I) -(V) , random telegraph noises, time-dependent defect spectroscopy, and TDDV accounting for the within-device fluctuation. These techniques, however, cannot be directly applied to SRAM, because their test conditions do not comply with typical SRAM operation. The central objective of this paper is to develop a technique suitable for characterizing both the negative BTI (NBTI) and positive BTI (PBTI) in SRAM. The key issues addressed include the SRAM relevant sensing Vg, measurement delay, capturing the upper envelope of degradation, sampling rate, and measurement time window. The differences between NBTI and PBTI are highlighted. The impact of NBTI and PBTI on the cell-level performance is assessed by simulation, based on experimental results obtained from individual devices. The simulation results show that, for a given static noise margin, test conditions have a significant effect on the minimum operation bias

Annual Survey of Virginia Law: Employment Law

This survey covers legislative and judicial developments in Virginia employment law between June 1986 and June 1987. It does not address the workers\u27 compensation and unemployment compensation statutes but focuses on state labor and fair employment laws and the employment-at-will doctrine

NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the 15 accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process

Microscopic origin of random telegraph noise fluctuations in aggressively scaled RRAM and its impact on read disturb variability

Random telegraph noise (RTN) is an important intrinsic phenomenon of any logic or memory device that is indicative of the reliability and stochastic variability in its performance. In the context of the resistive random access memory (RRAM), RTN becomes a key criterion that determines the read disturb immunity and memory window between the low (LRS) and high resistance states (HRS). With the drive towards ultra-low power memory (low reset current) and aggressive scaling to 10 × 10 nm2 area, contribution of RTN is significantly enhanced by every trap (vacancy) in the dielectric. The underlying mechanisms governing RTN in RRAM are yet to be fully understood. In this study, we aim to decode the role of conductance fluctuations caused by oxygen vacancy transport and inelastic electron trapping and detrapping processes. The influence of resistance state (LRS, shallow and deep HRS), reset depth and reset stop voltage (VRESET-STOP) on the conductance variability is also investigated. © 2013 IEEE

Identify the critical regions and switching/failure mechanisms in non-filamentary RRAM (a-VMCO) by RTN and CVS techniques for memory window improvement

Non-filamentary RRAM is a promising technology that features self-rectifying, forming/compliance-free, tight resistance distributions at both high and low resistance states (HRS/LRS). Direct experimental evidence for its physical switching & failure mechanisms, however, is still missing, due to the lack of suitable characterization techniques. In this work, a novel method combining the random-telegraph-noise (RTN), constant-voltagestress (CVS) and time-to-failure Weibull plot is developed to investigate these mechanisms in the non-filamentary RRAM cell based on amorphous-Si/TiO2. For the first time, the following key advances have been achieved: i) Switching mechanism by defect profile modulation in a critical interfacial region has been identified from defect locations extracted by RTN; ii) Defect profile in this region plays a critical role in device failure, leading to different Weibull distributions during negative (LRS) and positive (HRS) CVS; iii) Progressive formation of a conductive percolation path during electrical stress is directly observed due to defect generation in addition to pre-existing defect movement; iv) Optimizing the critical interfacial region significantly improves memory window and failure margin. This provides a useful tool for advancing the non-filamentary RRAM technology

Impact of Hot Carrier Aging on Random Telegraph Noise and Within a Device Fluctuation

For nanometer MOSFETs, charging and discharging a single trap induces random telegraph noise (RTN). When there are more than a few traps, RTN signal becomes complex and appears as within a device fluctuation (WDF). RTN/WDF causes jitters in switch timing and is a major challenge to low power circuits. In addition to RTN/WDF, devices also age. The interaction between RTN/WDF and aging is of importance and not fully understood. Some researchers reported aging increasing RTN/WDF, while others showed RTN/WDF being hardly affected by aging. The objective of this work is to investigate the impact of hot carrier aging (HCA) on the RTN/WDF of nMOSFETs. For devices of average RTN/WDF, it is found that the effect of HCA is generally modest. For devices of abnormally high RTN/WDF, however, for the first time, we report HCA reducing RTN/WDF substantially (>50%). This reduction originates from either a change of current distribution or defect losses

Impact of Hot Carrier Aging on Random Telegraph Noise and Within a Device Fluctuation

For nanometer MOSFETs, charging and discharging a single trap induces random telegraph noise (RTN). When there are more than a few traps, RTN signal becomes complex and appears as within a device fluctuation (WDF). RTN/WDF causes jitters in switch timing and is a major challenge to low power circuits. In addition to RTN/WDF, devices also age. The interaction between RTN/WDF and aging is of importance and not fully understood. Some researchers reported aging increasing RTN/WDF, while others showed RTN/WDF being hardly affected by aging. The objective of this work is to investigate the impact of hot carrier aging (HCA) on the RTN/WDF of nMOSFETs. For devices of average RTN/WDF, it is found that the effect of HCA is generally modest. For devices of abnormally high RTN/WDF, however, for the first time, we report HCA reducing RTN/WDF substantially (>50%). This reduction originates from either a change of current distribution or defect losses