Testbench qualification of SystemC TLM protocols through Mutation Analysis

Transaction-level modeling (TLM) has become the de-facto reference modeling style for system-level design and verification of embedded systems. It allows designers to implement high-level communication protocols for simulations up to 1000x faster than at register-transfer level (RTL). To guarantee interoperability between TLM IP suppliers and users, designers implement the TLM communication protocols by relying on a reference standard, such as the standard OSCI for SystemC TLM. Functional correctness of such protocols as well as their compliance to the reference TLM standard are usually verified through user-defined testbenches, which high-quality and completeness play a key role for an efficient TLM design and verification flow. This article presents a methodology to apply mutation analysis, a technique applied in literature for SW testing, for measuring the testbench quality in verifying TLM protocols. In particular, the methodology aims at (i) qualifying the testbenches by considering both the TLM protocol correctness and their compliance to a defined standard (i.e., OSCI TLM), (ii) optimizing the simulation time during mutation analysis by avoiding mutation redundancies, and (iii) driving the designers in the testbench improvement. Experimental results on benchmarks of different complexity and architectural characteristics are reported to analyze the methodology applicability

Learning to use gestures in narratives: developmental trends in formal and semantic gesture competence

This study analyses the way in which children develop their competence in the formal and semantic aspects of gesture. The analysis is focused upon the use of representational gestures in a narrative context. A group of 30 Italian children from 4 to 10 years was videotaped while telling a video cartoon to an adult. Gestures were coded according to the parameters used in Sign Languages analysis and analysed in terms of the acquisition of their properties, the accuracy of their execution and correctness in content representation.It was investigated also the development of the symbolic competence in relation both to the use of some of these parameters and to the representational strategies adopted. Results indicate a developmental trend in all the phenomena investigated and point out some formal similarities between gesture and Sign Languages

Reusing RTL assertion checkers for verification of SystemC TLM models

The recent trend towards system-level design gives rise to new challenges for reusing existing RTL intellectual properties (IPs) and their verification environment in TLM. While techniques and tools to abstract RTL IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still under-explored, particularly when ABV is adopted. Some frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet, except by using transactors to create a mixed simulation between the TLM design and the RTL checkers corresponding to the assertions. However, the use of transactors may lead to longer verification time due to the need of developing and verifying the transactors themselves. Moreover, the simulation time is negatively affected by the presence of transactors, which slow down the simulation at the speed of the slowest parts (i.e., RTL checkers). This article proposes an alternative methodology that does not require transactors for reusing assertions, originally defined for a given RTL IP, in order to verify the corresponding TLM model. Experimental results have been conducted on benchmarks with different characteristics and complexity to show the applicability and the efficacy of the proposed methodology

On the Reuse of RTL assertions in Systemc TLM Verification

Reuse of existing and already verified intellectual property (IP) models is a key strategy to cope with the com- plexity of designing modern system-on-chips (SoC)s under ever stringent time-to-market requirements. In particular, the recent trend towards system-level design and transaction level modeling (TLM) gives rise to new challenges for reusing existing RTL IPs and their verification environment in TLM-based design flows. While techniques and tools to abstract RTL IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still underexplored, particularly when assertion-based verification (ABV) is adopted. Some techniques and frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet. This paper proposes a methodology to reuse assertions originally defined for a given RTL IP, to verify the corresponding TLM model. Experimental results have been conducted on benchmarks of different characteristics and complexity to show the applicability and the efficacy of the proposed methodology

Mutual Guarantee Institutions (MGIs) and small business credit during the crisis

The recent economic and financial crisis has drawn attention to how mutual guarantee institutions (MGIs) facilitate small and medium enterprises in accessing bank financing. The aim of this paper is twofold. First, we describe the structural features of the Italian market for mutual guarantees and its significance for small business credit. To this end, we use extensive databases (the Central Credit Register and the Central Balance Sheet Register) as well as specific surveys, which allow us to fill information gaps about this industry and to quantify regional diversity. Second, we investigate whether MGIs’ support to small firms continued to be effective in 2008-09, when credit constraints to Italian firms peaked. We find that MGIs played a role in avoiding a break-up in credit flows to affiliated firms, which also benefited from a lower cost of credit. However, this came at the cost of a deterioration in credit quality, which was more intense for customers with guarantees from MGIs.microfinance, peer monitoring, small business finance

The Hyperphagia Questionnaire: Insights From a Multicentric Validation Study in Individuals With Prader Willi Syndrome

The present study aimed to validate the Italian version of the Hyperphagia Questionnaire (HQ), a 11-items questionnaire developed to assess hyperphagia in individuals with Prader-Willi syndrome (PWS). This is a complex neurodevelopmental disorder characterized by endocrine dysfunction, hypotonia, intellectual disability, psychiatric disorders and obesity