Quantum-mechanical communication theory

Optimum signal reception using quantum-mechanical communication theor

A 1.6 Gb/s, 3 mW CMOS receiver for optical communication

A 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-μm CMOS process. This receiver has no transimpedance amplifier and uses the parasitic capacitor of the flip-chip bonded photodetector as an integrating element and resolves the data with a double-sampling technique. A simple feedback loop adjusts a bias current to the average optical signal, which essentially "AC couples" the input. The resulting receiver resolves an 11 μA input, dissipates 3 mW of power, occupies 80 μm x 50 μm of area and operates at over 1.6 Gb/s

Venture capital support to small businesses

Supplementary Appendices 1-3 to report published by National Audit Office (HC: 23, 2009-10; ISBN: 9780102963304)This report looks at the Department’s programme of venture capital funds which 2 support small businesses seeking equity based finance. The scope of the report does not include Government provision of debt finance or tax incentives for small businesses, nor does it attempt to look in detail at “investment readiness” programmes within Government which assist small businesses in preparing their business plans so that they can pitch their propositions to investors more effectively.The National Audit Office commissioned Professor Gordon Murray supported by Dr Louis Liu of Exeter University to undertake a data collection exercise to allow the National Audit Office to understand the extent of publicly sponsored venture capital programmes in other countries

First Experimental Demonstration of Gate-all-around III-V MOSFET by Top-down Approach

The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a high mobility In0.53Ga0.47As channel and atomic-layer-deposited (ALD) Al2O3/WN gate stacks by a top-down approach. A well-controlled InGaAs nanowire release process and a novel ALD high-k/metal gate process has been developed to enable the fabrication of III-V GAA MOSFETs. Well-behaved on-state and off-state performance has been achieved with channel length (Lch) down to 50nm. A detailed scaling metrics study (S.S., DIBL, VT) with Lch of 50nm - 110nm and fin width (WFin) of 30nm - 50nm are carried out, showing the immunity to short channel effects with the advanced 3D structure. The GAA structure has provided a viable path towards ultimate scaling of III-V MOSFETs.Comment: IEEE IEDM 2011 pp. 769-772; Structures are valuable for low-dimensional physics stud