Super class AB RFC OTA with adaptive local common-mode feedback

A super class AB recycling folded cascode operational transconductance amplifier is presented. It employs local common-mode feedback using two matched tuneable active resistors, allowing to adapt the amplifier to different process variations and loads. Measurement results from a test chip prototype fabricated in a 0.5 μm CMOS process validate the proposal

CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

A CMOS fully integrated all-pass filter with an extremely low pole frequency of 2 Hz is introduced in this paper. It has 0.08-dB passband ripple and 0.029-mm 2 Si area. It has 0.38-mW power consumption in strong inversion with ±0.6-V power supplies. In subthreshold, it has 0.64-μW quiescent power and operates with ±200-mV dc supplies. Miller multiplication is used to obtain a large equivalent capacitor without excessive Si area. By varying the gain of the Miller amplifier, the pole frequency can be varied from 2 to 48 Hz. Experimental and simulation results of a test chip prototype in 130-nm CMOS technology validate the proposed circuit

Multi-Classification by Using Tri-Class SVM

The standard form for dealing with multi-class classification problems when biclassifiers are used is to consider a two-phase (decomposition, reconstruction) training scheme. The most popular decomposition procedures are pairwise coupling (one versus one, 1-v-1), which considers a learning machine for each Pair of classes, and the one-versus-all scheme (one versus all, 1-v-r), which takes into consideration each class versus the remaining classes. In this article a 1-v-1 tri-class Support Vector Machine (SVM) is presented. The expansion of the architecture of this machine into three categories specifically addresses the decomposition problem of how to prevent the loss of information which occurs in the usual 1-v-1 training procedure. The proposed machine, by means of a third class, allows all the information to be incorporated into the remaining training patterns when a multi-class problem is considered in the form of a 1-v-1 decomposition. Three general structures are presented where each improves some features from the precedent structure. In order to deal with multi-classification problems, it is demonstrated that the final machine proposed allows ordinal regression as a form of decomposition procedure. Examples and experimental results are presented which illustrate the performance of the new tri-class SV machine.Junta de Andalucía ACPAI-2003/014Ministerio de Ciencia y Tecnología TIC2002-04371-C02-0

Low-pH cement mortar-bentonite perturbations in a small-scale pilot laboratory experiment

This article has been published in a revised form in Clay Minerals [http://doi.org/10.1180/clm.2018.16]. This version is free to view and download for private research and study only. Not for re-distribution, re-sale or use in derivative worksA novel method to perform small-scale laboratory experiments that reproduce concrete–bentonite and concrete–groundwater interactions has been developed. Such interfaces will prevail in engineered barrier systems used for isolation of nuclear waste. With the goal of optimizing the experimental method, this work has analysed the geochemical interaction of distilled water, low-pH cement mortar and FEBEX-bentonite for 75 days. Limited but evident reactivity between the materials was observed, mainly decalcification in cement mortar, carbonation at the interface with bentonite and Mg enrichment in bentonite. These results are consistent with the state-of-the-art literature and were used to validate this small-scale pilot laboratory experiment to establish the basis for further studies comparing the behaviour of different buffer and cement materialsThe research leading to these results has received funding from the European Union's Horizon 2020 Research and Training 305 Programme of the EURATOM (H2020-NFRP-2014/2015) under grant agreement n° 662147 (CEBAMA

±0.25-V Class-AB CMOS Capacitance Multiplier and Precision Rectifiers

Reduction of minimum supply requirements is a crucial aspect to decrease the power consumption in VLSI systems. A high-performance capacitance multiplier able to operate with supplies as low as ±0.25 V is presented. It is based on adaptively biased class-AB current mirrors which provide high current efficiency. Measurement results of a factor 11 capacitance multiplier fabricated in 180-nm CMOS technology verify theoretical claims. Moreover, low-voltage precision rectifiers based on the same class-AB current mirrors are designed and fabricated in the same CMOS process. They generate output currents over 100 times larger than the quiescent current. Both proposed circuits have 300-nW static power dissipation when operating with ±0.25-V supplies

An Op-Amp Approach for Bandpass VGAs With Constant Bandwidth

Two approaches to implement variable gain amplifiers based on Miller op-amps are discussed. One has true constant bandwidth while the other has essentially reduced bandwidth variations with varying gain. Servo-loops and ac coupling techniques with quasi floating gate transistors are used to provide a bandpass response with very low cutoff frequency in the range of hertz. In practice, one of the schemes is shown to have bandwidth variations close to a factor two while the second one has true constant bandwidth over the gain tuning range. Experimental results of test chip prototypes in 180-nm CMOS technology verify the theoretical claims

±0.3V Bulk-Driven Fully Differential Buffer with High Figures of Merit

A high performance bulk-driven rail-to-rail fully differential buffer operating from ±0.3V supplies in 180 nm CMOS technology is reported. It has a differential–difference input stage and common mode feedback circuits implemented with no-tail, high CMRR bulk-driven pseudo-differential cells. It operates in subthreshold, has infinite input impedance, low output impedance (1.4 kΩ), 86.77 dB DC open-loop gain, 172.91 kHz bandwidth and 0.684 μW static power dissipation with a 50-pF load capacitance. The buffer has power efficient class AB operation, a small signal figure of merit FOMSS = 12.69 MHzpFμW−1, a large signal figure of merit FOMLS = 34.89 (V/μs) pFμW−1, CMRR = 102 dB, PSRR+ = 109 dB, PSRR− = 100 dB, 1.1 μV/√Hz input noise spectral density, 0.3 mVrms input noise and 3.5 mV input DC offset voltage.Junta de Andalucía - Consejería de Economía, Conocimiento, Empresas y Universidades P18-FR-4317Agencia Estatal de Investigación - FEDER PID2019-107258RB-C3

Low-Voltage 0.81mW, 1-32 CMOS VGA with 5% Bandwidth variations and 38dB DC rejection

A CMOS low-voltage amplifier with approximately constant bandwidth and DC rejection is introduced. The design is based on the cascade of a wide linear input range OTA, an op-amp and a servo-loop with extremely large time constants. It operates with ±0.45V supplies and a power consumption of 0.81mW in 180nm technology. The bandwidth changes only from 9.08MHz to 9.54MHz over a gain range from 1 to 32, it has a 9.8Hz low cutoff frequency and a DC attenuation of 38dBs. DC floating voltage sources are used to keep the gates of all differential pairs at a constant value close to a supply rail in order to operate the amplifier circuit with minimum supply voltage. The proposed circuit has small and large signal figures of merit FOM SS = 5380 (MHz*pF/mW) and FOM LS = 0.0085((V/ns)*pF/mA) for a nominal gain A = 32