The role of elasticity in slab bending

International audiencePrevious studies showed that plate rheology exerts a dominant control on the shape and velocity of subducting plates. Here, we perform a systematic investigation of the role of elasticity in slab bending, using fully dynamic 2-D models where an elastic, viscoelastic, or viscoelastoplastic plate subducts freely into a purely viscous mantle. We derive a scaling relationship between the bending radius of viscoelastic slabs and the Deborah number, De, which is the ratio of Maxwell time over deformation time. We show that De controls the ratio of elastically stored energy over viscously dissipated energy and find that at De>10-2, substantially less energy is required to bend a viscoelastic slab to the same shape as a purely viscous slab with the same intrinsic viscosity. Elastically stored energy at higher De favors retreating modes of subduction via unbending, while trench advance only occurs for some cases with De 1, where most zones have low De 0.1. Slabs with De<10-2 either have very low viscosities or they may be yielding, in which case our De estimates may be underestimated by up to an order of magnitude, potentially pointing towards a significant role of elasticity in ∼60% of the subduction zones. In support of such a role of elasticity in subduction, we find that increasing De correlates with increasing proportion of larger seismic events in both instrumental and historic catalogues

Multi-bit sigma-delta modulators with enhanced dynamic-range using non-linear DAC for hearing aids

15th IEEE International Conference on Electronics, Circuits and Systems, MaltaThis paper presents the possibility of employing nonlinear low-resolution DACs in the feedback paths of multi-bit second-order Sigma-Delta modulators. The proposed technique is particularly attractive in applications such as hearing aids, requiring a very large dynamic range and medium signal-tonoise-plus-distortion-ratio. As demonstrated through simulated results in which noise and mismatch effects are included, for the same over-sampling ratio, improvements in the order of 6-to-9 dB in the dynamic range can be achieved when comparing with the same topology employing linear-DACs

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUAA low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-and-Hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme

Digital-domain self-calibration technique for video-rate pipeline A/D converters using Gaussian white noise

Electronics Letters Vol.38, nº 19A digital-domain selfsalibmtion technique for video-rate pipeline AID converters based an a Gaussian white noise input signal is presented. The pmposed algorithm is simple and efficient. A design example is shown 10 illustrate that the overall linemiry of a pipeline ADC can be highly improved using this technique

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths

A FRAMEWORK TO SUPPORT SERVICE-ORIENTED ARCHITECTURE INVESTMENT DECISION

Service-oriented architecture (SOA) is a system paradigm that structures business functions as loosely coupled services to enable business agility. SOA requires significant up-front investments, and in return, promises a vast array of benefits. Unfortunately, in contrast to the costs of the investment, monetary benefits associated with SOA are more difficult to measure. For one reason, benefits such as increased agility or improved flexibility are elusive in nature, making it harder to define metrics for their calculation. For another, SOA value is realized in long term under uncertainty, and traditional capital budgeting methods often fail to capture uncertainty when valuing investments. In this paper, we provide a decision framework to analyze the monetary impact of SOA investment in an organization. Combining traditional NPV analysis with option pricing models, our framework accounts for operational and strategic costs and benefits of SOA and proposes an extended investment value to support managerial investment decision

New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification

15th IEEE International Conference on Electronics, Circuits and Systems, MaltaIn this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique

A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amplification

15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, PolóniaIn this paper a new structure for a multiplying-by-two amplifier is proposed. It is implemented by switching MOS capacitors with floating sources from inversion into depletion dropping the capacitance values in the amplification phase. Low-power is achieved since no operational amplifiers are required but, instead, simple sourcefollowers are used to provide the required isolation. Simulation results show that linearity levels better than 60dB and gain accuracies of better than 1.6% are achieved making this circuit well suited to be used in ultra low-power highspeed 6-to-8 bits pipeline or multi-stage algorithmic ADCs