Development of germanium/silicon integration for near infrared detection

Silicon (Si) is the base material for electronic technologies and is emerging as a very attractive platform for photonic integrated circuits (PICs). PICs allow optical systems to be made more compact with higher performance than discrete optical components. Applications for PICs are in the area of fibre-optic communication, biomedical devices, photovoltaics and imaging. Germanium (Ge), due to its suitable bandgap for telecommunications and its compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infrared wavelengths. There are two main approaches for Ge/Si integration: through epitaxial growth and through direct wafer bonding. The lattice mismatch of ~4.2% between Ge and Si is the main problem of the former technique which leads to a high density of dislocations while the bond strength and conductivity of the interface are the main challenges of the latter. Both result in trap states which are expected to play a critical role. Understanding the physics of the interface is a key contribution of this thesis. This thesis investigates Ge/Si diodes using these two methods. The effects of interface traps on the static and dynamic performance of Ge/Si avalanche photodetectors have been modelled for the first time. The thesis outlines the original process development and characterization of mesa diodes which were fabricated by transferring a ~700 nm thick layer of p-type Ge onto n-type Si using direct wafer bonding and layer exfoliation. The effects of low temperature annealing on the device performance and on the conductivity of the interface have been investigated. It is shown that the diode ideality factor and the series resistance of the device are reduced after annealing. The carrier transport mechanism is shown to be dominated by generation–recombination before annealing and by direct tunnelling in forward bias and band-to-band tunnelling in reverse bias after annealing. The thesis presents a novel technique to realise photodetectors where one of the substrates is thinned by chemical mechanical polishing (CMP) after bonding the Si-Ge wafers. Based on this technique, Ge/Si detectors with remarkably high responsivities, in excess of 3.5 A/W at 1.55 μm at −2 V, under surface normal illumination have been measured. By performing electrical and optical measurements at various temperatures, the carrier transport through the hetero-interface is analysed by monitoring the Ge band bending from which a detailed band structure of the Ge/Si interface is proposed for the first time. The above unity responsivity of the detectors was explained by light induced potential barrier lowering at the interface. To our knowledge this is the first report of light-gated responsivity for vertically illuminated Ge/Si photodiodes. The wafer bonding approach followed by layer exfoliation or by CMP is a low temperature wafer scale process. In principle, the technique could be extended to other materials such as Ge on GaAs, or Ge on SOI. The unique results reported here are compatible with surface normal illumination and are capable of being integrated with CMOS electronics and readout units in the form of 2D arrays of detectors. One potential future application is a low-cost Si process-compatible near infrared camera

Electronic and structural properties of rhombohedral [1 1 1] and [1 1 0] oriented ultra-thin bismuth nanowires

Structures and electronic properties of rhombohedral [1 1 1] and [1 1 0] bismuth nanowires are calculated with the use of density functional theory. The formation of an energy band gap from quantum confinement is studied and to improve estimates for the band gap the GW approximation is applied. The [1 1 1] oriented nanowires require surface bonds to be chemically saturated to avoid formation of metallic surface states, whereas the surfaces of the [1 1 0] nanowires do not support metallic surface states. It is found that the onset of quantum confinement in the surface passivated [1 1 1] nanowires occurs at larger critical dimensions than for the [1 1 0] nanowires. For the [1 1 1] oriented nanowires it is predicted that a band gap of ~0.5 eV can be formed at a diameter of approximately 6 nm, whereas for the [1 1 0] oriented nanowires a diameter of approximately 3 nm is required to achieve a similar band gap energy. The GW correction is also applied to estimates of the electron affinity, ionisation potentials and work functions for both orientations of the nanowires for various diameters below 5 nm. The magnitude of the energy band gaps that arise in bismuth at critical dimensions of a few nanometers are of the same order as for conventional bulk semiconductors

Comprehensive investigation of Ge-Si bonded interfaces using oxygen radical activation

In this work, we investigate the directly bonded germanium-silicon interfaces to facilitate the development of high quality germanium silicon hetero integration at the wafer scale. X-ray photoelectron spectroscopy data is presented which provides the chemical composition of the germanium surfaces as a function of the hydrophilic bonding reaction at the interface. The bonding process induced long range deformation is detected by synchrotron x-ray topography. The hetero-interface is characterized by measuring forward and reverse current, and by high resolution transmission electron microscopy. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3601355

A sub k(B)T/q semimetal nanowire field effect transistor

The key challenge for nanoelectronics technologies is to identify the designs that work on molecular length scales, provide reduced power consumption relative to classical field effect transistors (FETs), and that can be readily integrated at low cost. To this end, a FET is introduced that relies on the quantum effects arising for semimetals patterned with critical dimensions below 5 nm, that intrinsically has lower power requirements due to its better than a "Boltzmann tyranny" limited subthreshold swing (SS) relative to classical field effect devices, eliminates the need to form heterojunctions, and mitigates against the requirement for abrupt doping profiles in the formation of nanowire tunnel FETs. This is achieved through using a nanowire comprised of a single semimetal material while providing the equivalent of a heterojunction structure based on shape engineering to avail of the quantum confinement induced semimetal-to-semiconductor transition. Ab initio calculations combined with a non-equilibrium Green's function formalism for charge transport reveals tunneling behavior in the OFF state and a resonant conduction mechanism for the ON state. A common limitation to tunnel FET (TFET) designs is related to a low current in the ON state. A discussion relating to the semimetal FET design to overcome this limitation while providing less than 60 meV/dec SS at room temperature is provided

Toolbox of Advanced Atomic Layer Deposition Processes for Tailoring Large-Area MoS2 Thin Films at 150 °C

Two-dimensional MoS2 is a promising material for applications, including electronics and electrocatalysis. However, scalable methods capable of depositing MoS2 at low temperatures are scarce. Herein, we present a toolbox of advanced plasma-enhanced atomic layer deposition (ALD) processes, producing wafer-scale polycrystalline MoS2 films of accurately controlled thickness. Our ALD processes are based on two individually controlled plasma exposures, one optimized for deposition and the other for modification. In this way, film properties can be tailored toward different applications at a very low deposition temperature of 150 °C. For the modification step, either H2 or Ar plasma can be used to combat excess sulfur incorporation and crystallize the films. Using H2 plasma, a higher degree of crystallinity compared with other reported low-temperature processes is achieved. Applying H2 plasma steps periodically instead of every ALD cycle allows for control of the morphology and enables deposition of smooth, polycrystalline MoS2 films. Using an Ar plasma instead, more disordered MoS2 films are deposited, which show promise for the electrochemical hydrogen evolution reaction. For electronics, our processes enable control of the carrier density from 6 × 1016 to 2 × 1021 cm–3 with Hall mobilities up to 0.3 cm2 V–1 s–1. The process toolbox forms a basis for rational design of low-temperature transition metal dichalcogenide deposition processes compatible with a range of substrates and applications

Two-dimensional materials and their role in emerging electronic and photonic devices

Innovation in the field of semiconductor materials and devices have to a large extent underpinned the dramatic developments which have unfolded in the area of information and communication technologies over the past 50 years. The ability to form logic devices, memory elements, light emitting diodes, and lasers directly into semiconducting materials has had a transformative effect on modern society. Looking beyond the era of conventional scaling, the drive towards the internet of things, will require the integration of sensors and optical devices with conventional logic and memory elements. The aim of this article is to give a brief overview of the large-area growth of some 2D transition metal dichalcogenide layered materials by MBE and CVD methods, followed by examples of how these 2D materials can be employed in electron devices and optoelectronic structures and devices

Scrutinizing pre- and post-device fabrication properties of atomic layer deposition WS₂ thin films

In this work, we investigate the physical and electrical properties of WS2 thin films grown by a plasma-enhanced atomic layer deposition process, both before and after device fabrication. The WS2 films were deposited on thermally oxidized silicon substrates using the W(NMe2)2(NtBu)2 precursor and a H2S plasma at 450 °C. The WS2 films were approximately 8 nm thick, measured from high-resolution cross-sectional transmission electron imaging, and generally exhibited the desired horizontal basal-plane orientation of the WS2 layers to the SiO2 surface. Hall analysis revealed a p-type behavior with a carrier concentration of 1.31 × 1017 cm−3. Temperature-dependent electrical analysis of circular transfer length method test structures, with Ni/Au contacts, yielded the activation energy (Ea) of both the specific contact resistivity and the WS2 resistivity as 100 and 91 meV, respectively. The similarity of these two values indicates that the characteristics of both are dominated by the temperature dependence of the WS2 hole concentration. Change in the material, such as in sheet resistance, due to device fabrication is attributed to the chemicals and thermal treatments associated with resist spinning and baking, ambient and UV exposure, metal deposition, and metal lift off for contact pad formation.</p

Isotropic conduction and negative photoconduction in ultrathin PtSe2 films

PtSe2 ultrathin films are used as the channel of back-gated field-effect transistors that are investigated at different temperatures and under super-continuous white laser irradiation. The temperature-dependent behavior confirms the semiconducting nature of multilayer PtSe2, with p-type conduction, a hole field-effect mobility up to 40 cm2 V−1 s−1, and significant gate modulation. Electrical conduction measured along different directions shows isotropic transport. A reduction of PtSe2 channel conductance is observed under exposure to light. Such a negative photoconductivity is explained by a photogating effect caused by photo-charge accumulation in SiO2 and at the Si/SiO2 interface

Performance and reliability in back-gated CVD-grown MoS2 devices

In this work, the electrical performance and reliability of as-synthesized CVD-grown MoS2 transistors directly grown on SiO2/Si substrate without any transfer process have been evaluated. Transfer and output characteristics, current hysteresis, capacitancevoltage and low-frequency noise signatures have been characterized revealing the huge influence of surface and oxide defects and the disturbance due to the fluctuations of the carrier number on the back-gated transistor response.European Union’sHorizon 2020 research and innovation programme under theMarie Skłodowska-Curie grant agreement No 895322Spanish Government under Juan de la Cierva Formacion grantnumber FJC2018-038264-IThe Spanish Program (TEC2017-89800-R)ASCENT (EU Horizon 2020 GRANT 654384)Science Foundation Ireland: INVEST (SFI-15/IA/3131)Science Foundation Ireland: AMBER (12/RC/2278-P2

Characterization of germanium/silicon p-n junction fabricated by low temperature direct wafer bonding and layer exfoliation

The current transport across a p-Ge/n-Si diode structure obtained by direct wafer bonding and layer exfoliation is analysed. A low temperature anneal at 400 degrees C for 30 min was used to improve the forward characteristics of the diode with the on/off ratio at -1 V being > 8000. Post anneal, the transport mechanism has a strong tunnelling component. This fabrication technique using a low thermal budget (T <= 400 degrees C) is an attractive option for heterogeneous integration. (C) 2012 American Institute of Physics. (doi:10.1063/1.3688174