Twitter engagement model for the RecSys 2020 Challenge

Treballs finals del Màster de Fonaments de Ciència de Dades, Facultat de matemàtiques, Universitat de Barcelona, Any: 2020, Tutor: Santi Seguí MesquidaRecomendation systems is a wide field of research and it is present in many area of our daily life. The RecSys ACM conference is the most important conference in the recommendation area and each year it holds a competition, the RecSys Challenge. The work here presented aims to solve the RecSys 2020 Challenge which consists of giving a certain probability of two Twitter users to interact. We have developed a model which uses the power of Gradient Boosting Trees to combine multiple features we created to represent each interaction between users. Features such as popularity or engagement were combined with and embedding of the tweet text to create an interdisciplinary model that is able to reach 0.75 on the Precision-Recall area under the curve metric and 17.64 on the Relative Cross Entropy. The popularity feature and previous reactions to the same language were discovered as the most relevant features for our model. Regarding the competition, our team reached the ninth place of the challenge

Multi Look-Up Table Digital Predistortion for RF Power Amplifier Linearization

Premi extraordinari doctorat curs 2007-2008, àmbit d’Enginyeria de les TICAquesta Tesi Doctoral se centra en el disseny d'un nou linealitzador de Predistorsió Digital (Digital Predistortion - DPD) capaç de compensar la dinàmica i els efectes no lineals introduïts pels Amplificadors de Potència (Power Amplifiers - PAs). Un dels trets més rellevants d'aquest nou predistorsionador digital i adaptatiu consisteix en ser deduïble a partir d'un model de PA anomenat Nonlinear Auto-Regressive Moving Average (NARMA). A més, la seva arquitectura multi-LUT (multi-Taula) permet la implementació en un dispositiu Field Programmable Gate Array (FPGA).La funció de predistorsió es realitza en banda base, per tant, és independent de la banda freqüencial on es durà a terme l'amplificació del senyal de RF, el que pot resultar útil si tenim en compte escenaris multibanda o reconfigurables. D'altra banda, el fet que aquest DPD tingui en compte els efectes de memòria introduïts pel PA, representa una clara millora de les prestacions aconseguides per un simple DPD sense memòria. En comparació amb d'altres DPDs basats en models més computacionalment complexos, com és el cas de les xarxes neuronals amb memòria (Time-Delayed Neural Networks - TDNN), la estructura recursiva del DPD proposat permet reduir el nombre de LUTs necessàries per compensar els efectes de memòria del PA. A més, la seva estructura multi-LUT permet l'escalabilitat, és a dir, activar or desactivar les LUTs que formen el DPD en funció de la dinàmica que presenti el PA.En una primera aproximació al disseny del DPD, és necessari identificar el model NARMA del PA. Un dels majors avantatges que presenta el model NARMA és la seva capacitat per trobar un compromís entre la fidelitat en l'estimació del PA i la complexitat computacional introduïda. Per reforçar aquest compromís, l' ús d'algoritmes heurístics de cerca, com són el Simulated Annealing o els Genetic Algorithms, s'utilitzen per trobar els retards que millor caracteritzen la memòria del PA i per tant, permeten la reducció del nombre de coeficients necessaris per caracteritzar-la. Tot i així, la naturalesa recursiva del model NARMA comporta que, de cara a garantir l'estabilitat final del DPD, cal dur a terme un estudi previ sobre l'estabilitat del model.Una vegada s'ha obtingut el model NARMA del PA i s'ha verificat l'estabilitat d'aquest, es procedeix a l'obtenció de la funció de predistorsió a través del mètode d'identificació predictiu. Aquest mètode es basa en la continua identificació del model NARMA del PA i posteriorment, a partir del model obtingut, es força al PA perquè es comporti de manera lineal. Per poder implementar la funció de predistorsió en la FPGA, cal primer expressar-la en forma de combinacions en paral·lel i cascada de les anomenades Cel·les Bàsiques de Predistorsió (BPCs), que són les unitats fonamentals que composen el DPD. Una BPC està formada per un multiplicador complex, un port RAM dual que actua com a LUT (taula de registres) i un calculador d'adreces. Les LUTs s'omplen tenint en compte una distribució uniforme dels continguts i l'indexat d'aquestes es duu a terme mitjançant el mòdul de l'envoltant del senyal. Finalment, l'adaptació del DPD consisteix en monitoritzar els senyals d'entrada i sortida del PA i anar duent a terme actualitzacions periòdiques del contingut de les LUTs que formen les BPCs. El procés d'adaptació del contingut de les LUTs es pot dur a terme en la mateixa FPGA encarregada de fer la funció de predistorsió, o de manera alternativa, pot ser duta a terme per un dispositiu extern (com per exemple un DSP - Digital Signal Processor) en una escala de temps més relaxada. Per validar l'exposició teòrica i provar el bon funcionalment del DPD proposat en aquesta Tesi, es proporcionen resultats tant de simulació com experimentals que reflecteixen els objectius assolits en la linealització del PA. A més, certes qüestions derivades de la implementació pràctica, tals com el consum de potència o la eficiència del PA, són també tractades amb detall.This Ph.D. thesis addresses the design of a new Digital Predistortion (DPD) linearizer capable to compensate the unwanted nonlinear and dynamic behavior of power amplifiers (PAs). The distinctive characteristic of this new adaptive DPD is its deduction from a Nonlinear Auto Regressive Moving Average (NARMA) PA behavioral model and its particular multi look-up table (LUT) architecture that allows its implementation in a Field Programmable Gate Array (FPGA) device.The DPD linearizer presented in this thesis operates at baseband, thus becoming independent on the final RF frequency band and making it suitable for multiband or reconfigurable scenarios. Moreover, the proposed DPD takes into account PA memory effects compensation which representsan step forward in overcoming classical limitations of memoryless predistorters. Compared to more computational complex DPDs with dynamic compensation, such Time-Delayed Neural Networks (TDNN), this new DPD takes advantage of the recursive nature of the NARMA structure to relax the number of LUTs required to compensate memory effects in PAs. Furthermore, its parallel multi-LUT architecture is scalable, that is, permits enabling or disabling the contribution of specific LUTs depending on the dynamics presented by a particular PA.In a first approach, it is necessary to identify a NARMA PA behavioral model. The extraction of PA behavioral models for DPD linearization purposes is carried out by means of input and output complex envelope signal observations. One of the major advantages of the NARMA structure regards its capacity to deal with the existing trade-off between computational complexity and accuracy in PA behavioral modeling. To reinforce this compromise, heuristic search algorithms such the Simulated Annealing or Genetic Algorithms are utilized to find the best sparse delays that permit accurately reproducing the PA nonlinear dynamic behavior. However, due to the recursive nature of the NARMA model, an stability test becomes a previous requisite before advancing towards DPD linearization.Once the PA model is identified and its stability verified, the DPD function is extracted applying a predictive predistortion method. This identification method relies just on the PA NARMA model and consists in adaptively forcing the PA to behave as a linear device. Focusing in the DPD implementation, it is possible to map the predistortion function in a FPGA, but to fulfill this objective it is first necessary to express the predistortion function as a combined set of LUTs.In order to store the DPD function into a FPGA, it has to be stated in terms of parallel and cascade Basic Predistortion Cells (BPCs), which are the fundamental building blocks of the NARMA based DPD. A BPC is formed by a complex multiplier, a dual port RAM memory block acting as LUT and an address calculator. The LUT contents are filled following an uniform spacing procedure and its indexing is performed with the amplitude (modulus) of the signal's envelope.Finally, the DPD adaptation consists in monitoring the input-output data and performing frequent updates of the LUT contents that conform the BPCs. This adaptation process can be carried out in the same FPGA in charge of performing the DPD function, or alternatively can be performed by an external device (i.e. a DSP device) in a different time-scale than real-time operation.To support all the theoretical design and to prove the linearization performance achieved by this new DPD, simulation and experimental results are provided. Moreover, some issues derived from practical experimentation, such as power consumption and efficiency, are also reported and discussed within this thesis.Award-winningPostprint (published version

Workshops at IMS2023

Lists future events that should be of interest to practitioners and researchers.Peer ReviewedPostprint (published version

3-D distributed memory polynomial behavioral model for concurrent dual-band envelope tracking power amplifier linearization

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a new 3-D behavioral model to compensate for the nonlinear distortion arising in concurrent dual-band (DB) Envelope Tracking (ET) Power Amplifiers (PAs). The advantage of the proposed 3-D distributed memory polynomial (3D-DMP) behavioral model, in comparison to the already published behavioral models used for concurrent dual-band envelope tracking PA linearization, is that it requires a smaller number of coefficients to achieve the same linearity performance, which reduces the overall identification and adaptation computational complexity. The proposed 3D-DMP digital predistorter (DPD) is tested under different ET supply modulation techniques. Moreover, further model order reduction of the 3D-DMP DPD is achieved by applying the principal component analysis (PCA) technique. Experimental results are shown considering a concurrent DB transmission of aWCDMA signal at 1.75GHz and a 10-MHz bandwidth LTE signal at 2.1 GHz. The performance of the proposed 3D-DMP DPD is evaluated in terms of linearity, drain power efficiency, and computational complexity.Peer ReviewedPostprint (author's final draft

NPR shading evaluation on virtual reality

Treballs Finals de Grau d'Enginyeria Informàtica, Facultat de Matemàtiques, Universitat de Barcelona, Any: 2019, Director: Anna Puig Puig[en] Today, technology is evolving faster than ever. We are surrounded by in an endless number of new devices that try to recreate reality, and it is increasing, day by day, a more authentic immersion in game worlds. Virtual reality has recently experimented a boom and it does not look like this increasing trend is stopping any soon. It already has many different devices capable of using this technology and millions of consumers of this new reality all around the world. As you can imagine, the content visualized through the augmented reality glasses is not the same as the content that has been used for conventional computer games. This work proposes a set of metrics to objectively detect the quality of virtual reality images. To do this, a set of lighting techniques are implemented and afterwards analysed. Using these lighting techniques and generating a set of test images, we have been able to identify which visualization techniques are the most useful and well suited to be used in virtual reality

Computationally efficient real-time digital predistortion architectures for envelope tracking power amplifiers

This paper presents and discusses two possible real-time digital predistortion (DPD) architectures suitable for envelope tracking (ET) power amplifiers (PAs) oriented at a final computationally efficient implementation in a field programmable gate array (FPGA) device. In ET systems, by using a shaping function is possible to modulate the supply voltage according to different criteria. One possibility is to use slower versions of the original RF signal’s envelope in order to relax the slew-rate (SR) and bandwidth (BW) requirements of the envelope amplifier (EA) or drain modulator. The nonlinear distortion that arises when performing ET with a supply voltage signal that follows both the original and the slow envelope will be presented, as well as the DPD function capable of compensating for these unwanted effects. Finally, two different approaches for efficiently implementing the DPD functions, a polynomial-based and a look-up table-based, will be discussed.Peer ReviewedPostprint (published version

Dynamic selection and estimation of the digital predistorter parameters for power amplifier linearization

© © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a new technique that dynamically estimates and updates the coefficients of a digital predistorter (DPD) for power amplifier (PA) linearization. The proposed technique is dynamic in the sense of estimating, at every iteration of the coefficient's update, only the minimum necessary parameters according to a criterion based on the residual estimation error. At the first step, the original basis functions defining the DPD in the forward path are orthonormalized for DPD adaptation in the feedback path by means of a precalculated principal component analysis (PCA) transformation. The robustness and reliability of the precalculated PCA transformation (i.e., PCA transformation matrix obtained off line and only once) is tested and verified. Then, at the second step, a properly modified partial least squares (PLS) method, named dynamic partial least squares (DPLS), is applied to obtain the minimum and most relevant transformed components required for updating the coefficients of the DPD linearizer. The combination of the PCA transformation with the DPLS extraction of components is equivalent to a canonical correlation analysis (CCA) updating solution, which is optimum in the sense of generating components with maximum correlation (instead of maximum covariance as in the case of the DPLS extraction alone). The proposed dynamic extraction technique is evaluated and compared in terms of computational cost and performance with the commonly used QR decomposition approach for solving the least squares (LS) problem. Experimental results show that the proposed method (i.e., combining PCA with DPLS) drastically reduces the amount of DPD coefficients to be estimated while maintaining the same linearization performance.Peer ReviewedPostprint (author's final draft

Agnostic envelope linearization of dynamically supplied power amplifiers for mobile terminals

This paper presents an envelope linearization technique to compensate for the nonlinear distortion of envelope tracking (ET) power amplifiers (PAs) for 5G new radio (NR) mobile terminals. The proposed envelope optimization (EOPT) method is agnostic of the nonlinear distortion generated in the envelope supply path and can compensate for the nonlinear distortion at the ET PA output without the need to monitor the output at the envelope tracking modulator (ETM). The linearization system in the envelope path is based on the envelope generalized memory polynomial (EGMP) behavioral model. Since the ETM output is not available, an iterative nonlinear least squares solution inspired in the deep deterministic policy gradient (DDPG) algorithm is proposed to extract the coefficients of the EGMP model. The EOPT method is validated on a system-on-chip (SoC) ET PA board designed for mobile terminal applications. Experimental results show the suitability of the proposed method to guarantee the linearity requirements (i.e., adjacent channel power ratio below -36 dBc) with 16.8% of power efficiency when operating the ET PA with 5G new radio test signals of 60 MHz bandwidth operating at 2.55 GHz (band 7). The linearization performance of the proposed EOPT method is comparable to the envelope leakage cancellation (ELC) approach (but saving the need for an analog to digital converter to monitor the ETM output), and can outperform a conventional I-Q digital predistorter based on the generalized memory polynomial (GMP) behavioral model.This research was funded by Huawei Technologies from July 2020 to August 2021; and supported in part by the project PID2020-113832RB-C21 funded by MCIN/AEI/10.13039/50110001103 and in part by the Government of Catalonia and the European Social Fund under Grant 2021-FI-B-137.Peer ReviewedPostprint (published version

Spectral weighting orthogonal matching pursuit algorithm for enhanced out-of-band digital predistortion linearization

"© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works."This paper presents a new variant of the orthogonal matching pursuit (OMP) algorithm for reducing the computational complexity of the digital predistortion (DPD) behavioral model in the forward path. The proposed spectral weighting OMP (SW-OMP) algorithm focuses on selecting the most relevant basis functions to compensate for the out-of-band residual distortion which may eventually be masked by the dominant in-band residual error. This basis selection is carried out in an off-line process that does not affect the computational complexity of the real-time closed-loop DPD but, on the contrary, reduces its complexity while enhancing the robustness. Experimental results show that by selecting the DPD coefficients with the SW-OMP, the inherent ACLR and NMSE degradation suffered when reducing the number of coefficients is mitigated under strong nonlinear operation, when compared to using the basis functions selected by the classical OMP algorithm.Peer ReviewedPostprint (author's final draft

Multiple lookup table predistortion for adaptive modulation

This paper presents a multiple LUT digital adaptive predistorter based on a Hammerstein model that uses the return channel to feed back information from the receiver, concretely the bit error rate (BER), in order to train and later adapt the specific LUT gains that permit always operating at the best back-off level. This new predistorter architecture is aimed at coping with modern communication standards that use adaptive modulation (such as IEEE 802.11 or IEEE 802.16) and therefore continuously searching the best linear amplification to maximize power efficiency at the time that a certain quality of service (BER) in reception is guaranteed. Simulations provided will show the advantages of this multi-LUT configuration, where in front of different channel conditions, linear and efficient amplification (minimum back-off) is achieved at the time that a certain level of BER at reception is ensured. Index terms – Lookup tables (LUT), digital adaptive predistortion, Hammerstein models, adaptive modulation systems, peak to average power ratio (PAPR), bit error rate (BER).Peer Reviewe