Efficient hole-transporting layer MoO3:CuI deposited by co-evaporation in organic photovoltaic cells

In order to improve hole collection at the interface anode/electron donor in organic photovoltaic cells, it is necessary to insert a hole transporting layer. CuI was shown to be a very efficient hole transporting layer. However, its tendency to be quite rough tends to induce leakage currents and it is necessary to use a very slow deposition rate for CuI to avoid such negative effect. Herein, we show that the co-deposition of MoO3 and CuI avoids this difficulty and allows deposition of a homogeneous efficient hole-collecting layer at an acceptable deposition rate. Via an XPS study, we show that blending MoO3:CuI improves the hole collection efficiency through an increase of the gap state density. This increase is due to the formation of Mo5þ following interaction between MoO3 and CuI. Not only does the co-evaporation process allow for decreasing significantly the deposition time of the hole transporting layer, but also it increases the efficiency of the device based on the planar heterojunction, CuPc/C60

Ca/Alq3 hybrid cathode buffer layer for the optimization of organic solar cells based on a planar heterojunction

Use of efficient anode cathode buffer layer (CBL) is crucial to improve the efficiency of organic photovoltaic cells. Here we show that using a double CBL, Ca/Alq3, allows improving significantly cell performances. The insertion of Ca layer facilitates electron harvesting and blocks hole collection, leading to improved charge selectivity and reduced leakage current, whereas Alq3 blocks excitons. After optimisation of this Ca/Alq3 CBL using CuPc as electron donor, it is shown that it is also efficient when SubPc is substituted to CuPc in the cells. In that case we show that the morphology of the SubPc layer, and therefore the efficiency of the cells, strongly depends on the deposition rate of the SubPc film. It is necessary to deposit slowly (0.02 nm/s) the SubPc films because at higher deposition rate (0.06 nm/s) the films are porous, which induces leakage currents and deterioration of the cell performances. The SubPc layers whose formations are kinetically driven at low deposition rates are more uniform, whereas those deposited faster exhibit high densities of pinholes

Вивчення впливу високої температури на статичні характеристики 14 нм TG SOI N FinFET

Постійне масштабування розмірів польових транзисторів метал-оксид-напівпровідник (MOSFET) описується законом Мура, що призводить до розробки складних технологій електронних компонентів. Через труднощі масштабування планарного CMOS-транзистора з надією на збереження ефективногокерування каналом, пристрої FinFET були представлені для подолання різних проблем, таких як збільшення струму витоку, зменшення струму ввімкнення та погіршення коефіцієнта продуктивності. Пристрої FinFET мають інші важливі переваги перед планарними транзисторами, такі як зменшення випадкових флуктуацій легування та підвищення порогової напруги. Група BSIM продовжує розробляти моделі для комплементарної технології метал-оксид-напівпровідник, представляючи компактні моделі, що залежать від геометрії пристрою та не залежать від матеріалу, що є важливим для проектування електроніки. У даній роботі був досліджений вплив зміни температури від 77 до 377 K на вхідні та вихідні характеристики TG SOI N FinFET 14 нм. Мета дослідження полягає в аналізі впливу температури на порогову напругу, струми увімкнення та вимкнення, підпорогове коливання, зниження бар’єру, викликане стоком, та струм витоку. Berkeley PTM (Predictive Technology Model) використовується в інструментах SPICE і TCAD Atlas. При підвищенні температури від 77 до 377 К спостерігається погіршення співвідношення продуктивності ION/IOFF.The persistent scaling of feature sizes of metal–oxide–semiconductor field- effect transistors (MOSFETs) is described by Moore’s law which lead to the development of sophisticated electronic component technologies. Due to the difficulties in planar CMOS transistor scaling with the hope to preserve a good and acceptable channel control, FinFET devices have been introduced to overcome the different problems such as the increase of the leakage current, the decrease of the ON current and therefore the degradation of the performance ratio. FinFET devices have other important advantages over planar transistor such as reduced random doping fluctuation and the increase the threshold voltage. The BSIM Group continues to develop models for complementary metal–oxide–semiconductor technology by introducing device geometry-dependent, material-independent compact models which is essential for electronics designs. In this paper we investigate the effects of temperature variations from 77 to 377 K on the input and output characteristics of TG SOI N FinFET 14 nm. The aim of the study is to find out how temperature affects the threshold voltage, the ON and OFF currents, the Subthreshold Swing (SS), the Drain Induced Barrier Lowering and the leakage current. The Berkeley PTM (Predictive Technology Model) is used in SPICE and TCAD Atlas tools. While increasing the temperature from 77 to 377 K, the degradation of the performance ratio ION/IOFF is observed

Investigation of Some Physical Properties of Cobalt Doped MoO3 Nanofilms and Their Effects on the Degradation of the Methylene Blue Solution under UV Illumination

International audienc

Effect of Cu on InSe/Si(111) heterojunctions

The effect of sequential deposition of Cu onto a 300 Å-thick film of layered InSe epitaxially grown onto a Si(111) substrate, has been studied by Auger electron spectroscopy (AES), low energy electron diffraction (LEED) and photoemission yield spectroscopy (PYS). Cu coverages were from a few hundredth of a monolayer (in terms of InSe atomic surface plane: 1 ML = 7.2 × 1014 at/cm2, that is 0.85 Å of Cu-metal) to 300 ML. The effect of annealings up to 370 °C was also studied. It is shown that Cu has first a non uniform bulk interaction with InSe which looks like an insertion which saturates at 1 ML of Cu per In2Se2 single layer. Then it forms islands which fully mask the surface beyond about 150 ML coverage (130 Å of Cu-metal). Upon annealings beyond 300 °C, the Si substrate behaves as a Cu sink

Effect of 165-keV Ar-ion irradiation on microstructural and mechanical properties of zircaloy-4

Cold-worked zircaloy-4 was irradiated by 165 keV Ar ion at room temperature. The aim of the study is to understand the correlation between the dislocation loops induced by irradiation and material hardening. The results revealed ziracloy-4 swelling even at low dose and a strong lattice disorder along and directions. With increasing dose, the microstrain increases while the domain size decreases attributed to the dislocation loops formation. Nanohardness and dislocation density show a similar evolution with the dose, which demonstrate a good correlation between the two parameters. Consequently zircaloy-4 hardening observed at low dose is due to the dislocation loops formation

The effect of strontium doping on structural and morphological properties of ZnO nanofilms synthesized by ultrasonic spray pyrolysis method

International audienc

Photocatalytical properties of NiO nanofilms doped with Ba

International audienc

Efficient hole-transporting layer MoO 3 :CuI deposited by co-evaporation in organic photovoltaic cells

International audienc