TWEPP 2021 Topical Workshop on Electronics for Particle Physics

To meet new TDAQ buffering requirements and withstand the high expected radiation doses at the high-luminosity LHC, the ATLAS Liquid Argon Calorimeter readout electronics will be upgraded. Developments of low-power preamplifiers and shapers and of a low-power 40 MHz 14-bit ADCs are ongoing. The signals will be sent at 40 MHz to the off-detector electronics, where FPGAs connected through high-speed links will perform energy and time reconstruction. The data-processing, control and timing functions will be realized by dedicated boards. Results of tests of front-end component prototypes will be presented, along with design studies on the off-detector readout system

ARCHITECTURE ET CONCEPTION DE RETINES CMOS :<br />INTEGRATION DE LA MESURE DU MOUVEMENT GLOBAL<br />DANS UN IMAGEUR

In the early 90's, image sensors were dominated by CCD technology and CMOS sensors were only developed in research labs. Then a balance within the market shares has been reached thanks to the huge improvement in CMOS integrated circuits fabrication process. This is closely related to the emergence of portable devices like mobile phones, which most often embed photo or video functions. Indeed, such system integration in addition to cost constraints have favored CMOS technology. Nevertheless, video shots with these portable devices, very shaking prone, require a video stabilization which needs to estimate the inter frame global motion of sequences. Therefore, the goal of this work is to addthis function to the imagers fabricated by STMicroeletronics.To do so, a new global motion estimation technique is presented in this thesis. This method consists in extracting a global motion model from the local movements perceived in the periphery of images. This has been first validated by an algorithmic approach, before being integrated on silicon. The final architecture of the sensor has a photosensitive area divided into a central area and a peripheral one. The signal processing chain contains a pixel level processing to measure the peripheral local motions. It includes also a post-processingdedicated to the global motion model estimation and to the unwanted motion compensation.Les capteurs d'images CMOS n'étaient envisagés au début des années 90s que dans le cadre de recherches. La technologie CCD dominait alors. Puis l'évolution extraordinaire des procédés de fabrication de circuits intégrés CMOS a fait qu'aujourd'hui nous avons atteint une égalité en termes de parts du marché. Cette forte croissance est étroitement liée à l'avènement des dispositifs portables grand public tels que les téléphonesmobiles, qui embarquent pour la majorité les fonctions photo ou vidéo. En effet, les contraintes d'intégration et de coût favorisent la technologie CMOS. Cependant la prise de vue à l'aide de ces dispositifs portables, très sujets aux tremblements, nécessite une stabilisation de la vidéo qui implique d'estimer le mouvement global inter images. Aussi, l'objectif de ce travail est d'intégrer cette fonction aux imageurs fabriqués par la société STMicroelectronics.Pour ce faire, une technique novatrice pour estimer ce mouvement global est présentée dans ce mémoire. Cette méthode consiste à extraire un modèle du mouvement global à partir de mesures de déplacements locaux en périphérie des images. Elle a tout d'abord été validée defaçon algorithmique, avant d'être intégrée sur silicium. L'architecture finale du capteur se caractérise par une zone photosensible partitionnée en une zone centrale et une zone périphérique. La chaîne de traitement du signal comporte quant à elle un traitement au niveau pixel afin de mesurer les mouvements locaux périphériques. Elle comprend aussi un posttraitement dédié aux tâches d'estimation du modèle du mouvement global ainsi qu'à la compensation du mouvement indésiré

Architecture et conception de rétines silicium CMOS (intégration de la mesure du mouvement global dans un imageur)

MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF

Development of the ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

A new era of hadron collisions will start around 2027 with the High-Luminosity LHC, that will allow to collect ten times more data that what has been collected since 10 years at LHC. Five times higher instantaneous luminosity i.e. 8 billion collisions per second will happen. In order to withstand with the new specifications, the ATLAS Liquid Argon Calorimeter readout electronics will be upgraded during the 2025-2027 shutdown. Four subsets of the whole readout chain are concerned and are described here. Two of them are front-end electronics dedicated to the precise sensing of the detector cells, the digitization, the serialization and the optical transfer of the data to the off-detector electronics. The front-end electronics has to be tolerant to radiation up to 140 krad. The first subset is the new front-end board. It will amplify, shape and digitize on two gains the ionization calorimeter signal. Multiple silicon circuits have been designed for this purpose. The second is the new calibration board which will allow the precise calibration of all 182 500 channels of the calorimeter by injecting well known amplitude and shape pulses. The off-detector electronics is also made of two subsets. One is taking care in distributing the timing, trigger and control interface to the on-detector electronics. The other handles to process the huge data bandwidth coming from the 1524 front-end boards ie. 31912 optical fiber at 10.24 Gbps ~ 320 Tbps to compute signal energy, time-stamping and send the data to the online processing system

Development of the ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

A new era of hadron collisions will start around 2027 with the High-Luminosity LHC, that will allow to collect ten times more data that what has been collected since 10 years at LHC. This is at the price of higher instantaneous luminosity and higher number of collisions per bunch crossing. In order to withstand the high expected radiation doses, the ATLAS Liquid Argon Calorimeter readout electronics will be upgraded. The electronic readout chain is made of 4 main parts. The new front-end board will allow to amplify, shape and digitise on two gains the ionisation calorimeter signal over a dynamic range of 16 bits and 11 bit precision. Low noise below Minimum Ionising Particle (MIP), i.e below 120 nA for 45 ns peaking time, and maximum non-linearity of two per mil are required. Custom low noise preamplifier and shaper are being developed to meet these requirements using 65 nm and 130 nm CMOS technologies. They should be stable under irradiation until 1.4kGy (TID) and 4.1x10^13 new/cm^2 (NIEL). Two concurrents preamp-shaper ASICs have been developed and the best one in term of noise has been chosen. The test results of the new version of this ASIC will be presented. A new ADC chip prototype has been also submitted in June. Integration tests of the different components (including lpGBT links developed by CERN) on a 32-channels front-end board are ongoing, and results of this integration will be also shown. The new calibration board will allow the precise calibration of all 128000 channels of the calorimeter over a 16 bits dynamic range. A non-linearity of one per mil and non-uniformity between channels of 0.25% with a pulse rise time smaller than 1ns should be achieved. In addition, the custom calibration ASICs should be stable under irradiation with same levels as preamp-shaper and ADC chips. The HV SOI CMOS XFAB 180nm technology is used for the pulser ASIC, while the TSMC 130 nm technology is now used for the DAC part. During second prototype testing, it was found that the DAC part of the calibration system, inserted previously with the pulser in XFAB 180nm technology, was not rad-hard, already after 0.5 kGy. This is why a third version has been designed overcoming this issue, and all results will be presented. The data are sent off-detector at 40 MHz where FPGAs connected through high-speed links will perform energy and time reconstruction through the application of corrections and digital filtering. The off-detector electronics receive 345 Tbps from front-end readout, which require 33000 links at 10 Gbps. For the first time, online machine learning technics are used in the FPGAs in order to better filter the data. The first test results of the signal processing board will be shown. Reduced data are then sent with low latency to the first level trigger, while the full data are buffered until the reception of trigger accept signals. The data-processing, control and timing functions are realized by dedicated boards connected through ATCA crates. Design status of this timing boards will be shown too

An Integrated Image Motion Sensor for Micro Camera Module

International audienceThis paper deals with the building of a vision sensor which provides standard video capture and the associated global motion between consecutive frames. We aim at proposing embedded solutions for mobile applications. The application we focus on is video stabilization. Therefore the global motion we consider here is the one typically produced by handheld devices movement. We extract this global motion from local motion measures at the periphery of the image acquisition area. Thanks to this peculiar and “taskoriented” configuration, we take advantage of CMOS focal plane processing capabilities without sacrificing the sensor fill factor. We have at first validated the technique by software. Then we have designed peripheral custom pixels dedicated to motion detection and we are implementing it in a CMOS 0.13µm technology

Pixel Level Silicon Integration of Motion Estimation

International audienc

MAPSSIC, a Novel CMOS Intracerebral Positrons Probe for Deep Brain Imaging in Awake and Freely Moving Rats: A Monte Carlo Study

International audiencePreclinical behavior neuroimaging gathers simultaneous assessment of behavior and functional brain imaging. It is a potential key breakthrough to improve the understanding of brain processes and assess the validity of preclinical studies in drug development. Achieving such a combination is difficult, anesthesia or restraints inherent to conventional nuclear imaging preclude its use for behavior studies. In that context, we have proposed an original strategy using submillimetric probes to directly measures positrons inside the rat brain. This paper gives the results of Monte Carlo simulations of a new generation of intracerebral positron probe based on a CMOS Monolithic Active Pixel Sensor. We present the results obtained for a probe into a large homogeneous volume of radioactive water (18 F) leading to a sensitivity of 0.88 cps · Bq −1 · mm 3 and a mean energy deposition by positrons of 15.1 keV. Simulation in simplified brain-shaped sources modeling a 11 C-raclopride experiment shows that the implanted volume modeling the left putamen contribute to 92.4 % of the signal from positrons. We also investigate the effects of the thickness of the sensitive layer, the energy threshold and pixel dimensions on the detection capacities of the sensor. We demonstrate that an increase in the sensitive thickness from 18 to 190 µm would lead to an increase of positrons sensitivity by a factor of 1.74, but to a decrease of the direct (positrons) to indirect (γ-rays and electrons) sensitivity ratio by a factor of 1.59. Finally we show that for a threshold lower than about 5 keV the effect of the pixel dimensions is negligible

Submission of the first fullscale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the View the MathML source0.25μm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80×336 pixels, each View the MathML source50×250μm2, consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL

The FE-I4 Pixel Readout Chip and the IBL Module

FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept