Simulated Hough Transform Model Optimized for Straight-Line Recognition Using Frontier FPGA Devices

The use of the Hough transforms to identify shapes or images has been extensively studied in the past using software for artificial intelligence applications. In this article, we present a generalization of the goal of shape recognition using the Hough transform, applied to a broader range of real problems. A software simulator was developed to generate input patterns (straight-lines) and test the ability of a generic low-latency system to identify these lines: first in a clean environment with no other inputs and then looking for the same lines as ambient background noise increases. In particular, the paper presents a study to optimize the implementation of the Hough transform algorithm in programmable digital devices, such as FPGAs. We investigated the ability of the Hough transform to discriminate straight-lines within a vast bundle of random lines, emulating a noisy environment. In more detail, the study follows an extensive investigation we recently conducted to recognize tracks of ionizing particles in high-energy physics. In this field, the lines can represent the trajectories of particles that must be immediately recognized as they are created in a particle detector. The main advantage of using FPGAs over any other component is their speed and low latency to investigate pattern recognition problems in a noisy environment. In fact, FPGAs guarantee a latency that increases linearly with the incoming data, while other solutions increase latency times more quickly. Furthermore, HT inherently adapts to incomplete input data sets, especially if resolutions are limited. Hence, an FPGA system that implements HT is inefficient for small sets of input data but becomes more cost-effective as the size of the input data increases. The document first presents an example that uses a large Accumulator consisting of 1100 x 600 Bins and several sets of input data to validate the Hough transform algorithm as random noise increases to 80% of input data. Then, a more specifically dedicated input set was chosen to emulate a real situation where a Xilinx UltraScale+ was to be used as the final target device. Thus, we have reduced the Accumulator to 280 x  280 Bins using a clock signal at 250 MHz and a few tens input points. Under these conditions, the behavior of the firmware matched the software simulations, confirming the feasibility of the HT implementation on FPGA

A high throughput Intrusion Detection System (IDS) to enhance the security of data transmission among research centers

Data breaches and cyberattacks represent a severe problem in higher education institutions and universities that can result in illegal access to sensitive information and data loss. To enhance the security of data transmission, Intrusion Prevention Systems (IPS, i.e., firewalls) and Intrusion Detection Systems (IDS, i.e., packet sniffers) are used to detect potential threats in the exchanged data. IPSs and IDSs are usually designed as software programs running on a server machine. However, when the speed of exchanged data is too high, this solution can become unreliable. In this case, IPSs and IDSs designed on a real hardware platform, such as ASICs and FPGAs, represent a more reliable solution. This paper presents a packet sniffer that was designed using a commercial FPGA development board. The system can support a data throughput of 10 Gbit/s with preliminary results showing that the speed of data transmission can be reliably extended to 100 Gbit/s. The designed system is highly configurable by the user and can enhance the data protection of information transmitted using the Ethernet protocol. It is particularly suited for the security of universities and research centers, where point-to-point network connections are dominant and large amount of sensitive data are shared among different hosts.Comment: 10 pages, 10 figures, 16th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD23), 25-29 September 2023, Siena, Ital

Direct constraints on the top-Higgs coupling from the 8 TeV LHC data

The LHC experiments have analyzed the 7 and 8 TeV LHC data in the main Higgs production and decay modes. Current analyses only loosely constrain an anomalous top-Higgs coupling in a direct way. In order to strongly constrain this coupling, the Higgs-top associated production is reanalyzed. Thanks to the strong destructive interference in the t-channel for standard model couplings, this process can be very sensitive to both the magnitude and the sign of a non-standard top-Higgs coupling. We project the sensitivity to anomalous couplings to the integrated luminosity of 50 fb^{-1}, corresponding to the data collected by the ATLAS and CMS experiments in 7 and 8 TeV collisions, as of 2012. We show that the combination of di-photon and multi-lepton signatures, originating from different combinations of the top and Higgs decay modes, can be a potential probe to constrain a large portion of the negative top-Higgs coupling space presently allowed by the ATLAS and CMS global fits.Comment: 21 pages, 4 figures; a few reducible backgrounds included, final results unchanged, to appear in JHE

Nanoparticle-based receptors mimic protein-ligand recognition

The self-assembly of a monolayer of ligands on the surface of noble metal nanoparticles dictates the fundamental nanoparticle\u2019s behavior and its functionality. In this combined computational\u2013experimental study, we analyze the structure, organization, and dynamics of functionalized coating thiols in monolayer-protected gold nanoparticles (AuNPs). We explain how functionalized coating thiols self-organize through a delicate and somehow counterintuitive balance of interactions within the monolayer itself and with the solvent. We further describe how the nature and plasticity of these interactions modulate nanoparticle-based chemosensing. Importantly, we found that self-organization of coating thiols can induce the formation of binding pockets in AuNPs. These transient cavities can accommodate small molecules, mimicking protein-ligand recognition, which may explain the selectivity and sensitivity observed for different organic analytes in NMR chemosensing experiments. Thus, our findings advocate for the rational design of tailored coating groups to form specific recognition binding sites on monolayer-protected AuNPs

Validation and uncertainty analysis of ASTEC in early degradation phase against QUENCH-06 experiment

Two pyrene-tetrazole conjugates were synthesized as photoreactive chromophores that allow for the first time the combination of metabolic labelling of DNA in cells and subsequent bioorthogonal “photoclick” modification triggered by visible light. Two strained alkenes and three alkene-modified nucleosides were used as reactive counterparts and revealed no major differences in their “photoclick” reactivity. This is a significant advantage because it allows 5-vinyl-2′-deoxyuridine to be applied as the smallest possible alkene-modified nucleoside for metabolic labelling of DNA in cells. Both pyrene-tetrazole conjugates show fluorogenicity during the “photoclick” reactions, which is a second advantage for cellular imaging. Living HeLa cells were incubated with 5-vinyl-2′-deoxyuridine for 48 h to ensure one cell division. After fixation, the newly synthesized genomic DNA was successfully labelled by irradiation with visible light at 405 nm and 450 nm. This method is an attractive tool for the visualization of genomic DNA in cells with full spatiotemporal control by the use of visible light as a reaction trigger

General purpose readout board {\pi} LUP: overview and results

This work gives an overview of the PCI-Express board $\pi$LUP, focusing on the motivation that led to its development, the technological choices adopted and its performance. The $\pi$LUP card was designed by INFN and University of Bologna as a readout interface candidate to be used after the Phase-II upgrade of the Pixel Detector of the ATLAS and CMS experiments at LHC. The same team in Bologna is also responsible for the design and commissioning of the ReadOut Driver (ROD) board - currently implemented in all the four layers of the ATLAS Pixel Detector (Insertable B-Layer, B-Layer, Layer-1 and Layer-2) - and acquired in the past years expertise on the ATLAS readout chain and the problematics arising in such experiments. Although the $\pi$LUP was designed to fulfill a specific task, it is highly versatile and might fit a wide variety of applications, some of which will be discussed in this work. Two 7$^{th}$-generation Xilinx FPGAs are mounted on the board: a Zynq-7 with an embedded dual core ARM Processor and a Kintex-7. The latter features sixteen 12.5$\,$Gbps transceivers, allowing the board to interface easily to any other electronic board, either electrically and/or optically, at the current bandwidth of the experiments for LHC. Many data-transmission protocols have been tested at different speeds, results will be discussed later in this work. Two batches of $\pi$LUP boards have been fabricated and tested, two boards in the first batch (version 1.0) and four boards in the second batch (version 1.1), encapsulating all the patches and improvements required by the first version.Comment: 6 pages, 10 figures, 21th Real Time Conference, winner of "2018 NPSS Student Paper Award Second Prize