Spin transport and spin torque in antiferromagnetic devices

Ferromagnets are key materials for sensing and memory applications. In contrast, antiferromagnets which represent the more common form of magnetically ordered materials, have found less practical application beyond their use for establishing reference magnetic orientations via exchange bias. This might change in the future due to the recent progress in materials research and discoveries of antiferromagnetic spintronic phenomena suitable for device applications. Experimental demonstration of the electrical switching and detection of the Néel order open a route towards memory devices based on antiferromagnets. Apart from the radiation and magnetic-field hardness, memory cells fabricated from antiferromagnets can be inherently multilevel, which could be used for neuromorphic computing. Switching speeds attainable in antiferromagnets far exceed those of ferromagnetic and semiconductor memory technologies. Here we review the recent progress in electronic spin-transport and spin-torque phenomena in antiferromagnets that are dominantly of the relativistic quantum mechanical origin. We discuss their utility in pure antiferromagnetic or hybrid ferromagnetic/antiferromagnetic memory devices

A low-cost digital frequency testing approach for mixed-signal devices using ΣΔ modulation

This paper presents a digital approach to frequency testing of Analogue and mixed-signal (AMS) circuits. This approach is aimed at facilitating low-cost test techniques for system-on-chip (SoC) devices, rendering the test of mixed-signal cores compatible with the use of a low-cost digital tester. Analogue test signal generation is performed on-chip by low pass filtering a sigma-delta (ΣΔ) encoded bit-stream. Analogue harmonic test response analysis is also performed on-chip using square wave modulation and ΣΔ modulation. Since both analogue signal generation and test response analysis are digitally programmable on-chip, compatibility with a low-cost digital tester is ensured. Optimisation of test signatures is discussed in detail as a trade-off between fault and yield coverage. A 0.18 μm CMOS implementation of this BIST technique is presented, including some experimental results. © 2005 Elsevier Ltd. All rights reserved.This work has been realised in the frame of the MEDEA+European project T-101 TechnoDat, in cooperation with ST Microelectronics. The funding provided by Ministère de l'Economie et des Finances is gratefully acknowledged.Peer Reviewe

Comparison of Verilog-A compact modelling strategies for spintronic devices

International audienc

Spin Orbit Torque memory for non-volatile microprocessor caches

Magnetic spin-based memory technologies are a promising solution to overcome the incoming limits of microelectronics. Nevertheless, the long write latency and high write energy of these memory technologies compared to SRAM make it difficult to use these for fast microprocessor memories, such as L1- Caches. However, the recent advent of the Spin Orbit Torque (SOT) technology changed the story: indeed, it potentially offers a writing speed comparable to SRAM with a much better density as SRAM and an infinite endurance, paving the way to a new paradigm in processor architectures, with introduction of non- volatility in all the levels of the memory hierarchy towards full normally-off and instant-on processors. This paper presents a full design flow, from device to system, allowing to evaluate the potential of SOT for microprocessor cache memories and very encouraging simulation results using this framework

A built-in I-DDQ testing circuit

Although I-DDQ testing has become a widely accepted defect detection technique for CMOS ICs, its effectiveness in very deep submicron technologies is threatened by the increased transistor leakage current. In this paper, a built-in IDDQ testing circuit is presented, that aims to extend the viability Of IDDQ testing in future technologies and first experimental results are discussed

Cmp-Pim: An Energy-Efficient Comparator-Based Processing-In-Memory Neural Network Accelerator

In this paper, an energy-efficient and high-speed comparator-based processing-in-memory accelerator (CMP-PIM) is proposed to efficiently execute a novel hardware-oriented comparator-based deep neural network called CMPNET. Inspired by local binary pattern feature extraction method combined with depthwise separable convolution, we first modify the existing Convolutional Neural Network (CNN) algorithm by replacing the computationally-intensive multiplications in convolution layers with more efficient and less complex comparison and addition. Then, we propose a CMP-PIM that employs parallel computational memory sub-array as a fundamental processing unit based on SOT-MRAM. We compare CMP-PIM accelerator performance on different data-sets with recent CNN accelerator designs. With the close inference accuracy on SVHN data-set, CMP-PIM can get ∼ 94× and 3× better energy efficiency compared to CNN and Local Binary CNN (LBCNN), respectively. Besides, it achieves 4.3× speed-up compared to CNN-baseline with identical network configuration