Shopping online using the mobile channel: drivers of buying behaviour for Chinese consumers

The emergence of online channels is opening up to new research topics in the retailing literature. Particularly in China, the multifunctional mobile retailing apps, allowing to buy online and socialize the shopping activity with relatives, friends and followers, are supporting the spread of online shopping. A structural equation model combining both traditional antecedents of online shopping - such as ease of use, time convenience, perceived risk - with emerging drivers like perceived price differentiation and shopping socialization is tested to measure the intention to buy using a smartphone by Chinese people. Empirical findings offer new insights for both scholars and practitioners

Capacità dinamiche e vantaggio competitivo: un’analisi empirica nel retail

Obiettivi. L’articolo studia il tema delle capacità dinamiche nel retail, verificando l’impatto delle sue componenti sulle performance competitive di un campione di piccoli imprenditori commerciali al dettaglio. Metodologia. La ricerca è stata svolta somministrando un questionario strutturato ad un campione di imprenditori commerciali al dettaglio. I dati raccolti sono stati elaborati applicando una regressione lineare multipla. Risultati. Le evidenze empiriche mostrano come la creazione di conoscenza e di integrazione della stessa impattano in modo significativo e positivo sulle performance competitive, mentre capacità dinamiche legate a processi strutturati di apprendimento e riconfigurazione delle risorse agiscono in senso opposto. Limiti della ricerca. L’articolo esplora come le capacità dinamiche impattano sulle performance di piccoli imprenditori industriali al dettaglio; l’originalità dell’analisi e i pochi studi empirici di riferimento circoscrivono la lettura degli effetti evidenziati, che richiedono ulteriori approfondimenti. Implicazioni pratiche. I piccoli imprenditori commerciali al dettaglio in sede fissa dovrebbero puntare sulla capacità di innovare la propria offerta, rivedendola sia in termini di assortimento offerto che di servizio erogato, migliorando la capacità di alimentare un network con i propri stakeholder, fornitori e clienti in primis. Originalità del lavoro. Ad oggi la letteratura di retail ha scarsamente investigato il tema delle capacità dinamiche, rari sono gli studi empirici sul tema e limitati ad indagini di tipo qualitativo con finalità sostanzialmente esplorative. Il paper intende contribuire a colmare tali gap con una ricerca originale, sulla base di una raccolta dati ad hoc

Generalized hole-particle transformations and spin reflection positivity in multi-orbital systems

We propose a scheme combining spin reflection positivity and generalized hole-particle and orbital transformations to characterize the symmetry properties of the ground state for some correlated electron models on bipartite lattices. In particular, we rigorously determine at half-filling and for different regions of the parameter space the spin, orbital and $\eta$ pairing pseudospin of the ground state of generalized two-orbital Hubbard models which include the Hund's rule coupling.Comment: 6 pages, 2 figure

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

A sensitive one-step real-time PCR for detection of avian influenza viruses using a MGB probe and an internal positive control

BACKGROUND: Avian influenza viruses (AIVs) are endemic in wild birds and their introduction and conversion to highly pathogenic avian influenza virus in domestic poultry is a cause of serious economic losses as well as a risk for potential transmission to humans. The ability to rapidly recognise AIVs in biological specimens is critical for limiting further spread of the disease in poultry. The advent of molecular methods such as real time polymerase chain reaction has allowed improvement of detection methods currently used in laboratories, although not all of these methods include an Internal Positive Control (IPC) to monitor for false negative results. Therefore we developed a one-step reverse transcription real time PCR (RRT-PCR) with a Minor Groove Binder (MGB) probe for the detection of different subtypes of AIVs. This technique also includes an IPC. METHODS: RRT-PCR was developed using an improved TaqMan technology with a MGB probe to detect AI from reference viruses. Primers and probe were designed based on the matrix gene sequences from most animal and human A influenza virus subtypes. The specificity of RRT-PCR was assessed by detecting influenza A virus isolates belonging to subtypes from H1–H13 isolated in avian, human, swine and equine hosts. The analytical sensitivity of the RRT-PCR assay was determined using serial dilutions of in vitro transcribed matrix gene RNA. The use of a rodent RNA as an IPC in order not to reduce the efficiency of the assay was adopted. RESULTS: The RRT-PCR assay is capable to detect all tested influenza A viruses. The detection limit of the assay was shown to be between 5 and 50 RNA copies per reaction and the standard curve demonstrated a linear range from 5 to 5 × 10(8 )copies as well as excellent reproducibility. The analytical sensitivity of the assay is 10–100 times higher than conventional RT-PCR. CONCLUSION: The high sensitivity, rapidity, reproducibility and specificity of the AIV RRT-PCR with the use of IPC to monitor for false negative results can make this method suitable for diagnosis and for the evaluation of viral load in field specimens

Long-term efficacy of boosted and unboosted atazanavir-containing regimens: results from the SCOLTA project

In this study we evaluated the efficacy of boosted and unboosted ATV in different regimens in a cohort of HIV-1 infected patients

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 7 64 pixels with 50 \ub5m 7 50 \ub5m pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irradiation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends performance after irradiation. First sample chips have been also bump-bonded to 50 \ub5m 7 50 \ub5m and single readout electrode 25 \ub5m 7 100 \ub5m 3D sensors provided by Trento FBK. This represented a major milestone for the entire CHIPIX65 project, offering to the pixel community the first example of a complete readout chip in 65 nm CMOS technology coupled to such a kind of silicon detectors. Extensive characterizations with laser and radioactive sources have started. This paper briefly summarizes most important pre- and post-irradiation results, along with preliminary results obtained from chips bump-bonded to 3D sensors. Selected components of the CHIPIX65 demonstrator have been finally integrated into the large-scale RD53A prototype submitted at the end of summer 2017 by the CERN RD53 international collaboration on 65 nm CMOS technology

RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC

Pixel detectors at HL-LHC experiments will be exposed to unprecedented level of radiation and particle flux. This paper describes the program of development of an innovative pixel chip using a CMOS 65nm technology for the first time in HEP community, for experiments with extreme particle rates and radiation at future High Energy Physics colliders. The RD53 collaboration effort is described together with the CHIPIX65 INFN project

Design of analog front-ends for the RD53 demonstrator chip

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment