On-Going Radiation Effects on FPGAs - Lessons Learned and Plans

No abstract availabl

Effect of Radiation Exposure on the Retention of Commercial NAND Flash Memory

We have compared the data retention of irradiated commercial NAND flash memories with that of unirradiated controls. Under some circumstanc es, radiation exposure has a significant effect on the retention of f lash memories

Incorporating Probability Models of Complex Test Structures to Perform Technology Independent FPGA Single Event Upset Analysis

We present SEU test and analysis of the Microsemi ProASIC3 FPGA. SEU Probability models are incorporated for device evaluation. Included is a comparison to the RTAXS FPGA illustrating the effectiveness of the overall testing methodology

Enhancing Observability of Signal Composition and Error Signatures During Dynamic SEE Analog to Digital Device Testing

A novel approach to dynamic SEE ADC testing is presented. The benefits of this test scheme versus prior implemented techniques include the ability to observe ADC SEE errors that are in the form of phase shifts, single bit upsets, bursts of disrupted signal composition, and device clock loss

TID and SEE Response of an Advanced Samsung 4G NAND Flash Memory

Initial total ionizing dose (TID) and single event heavy ion test results are presented for an unhardened commercial flash memory, fabricated with 63 nm technology. Results are that the parts survive to a TID of nearly 200 krad (SiO2), with a tractable soft error rate of about 10(exp -l2) errors/bit-day, for the Adams Ten Percent Worst Case Environment

Effectiveness of Internal vs. External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis

We compare two scrubbing mitigation schemes for Xilinx FPGA devices. The design of the scrubbers is briefly discussed along with an examination of mitigation limitations. Proton and Heavy Ion data are then presented and analyzed

Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer

Ultra-Scaled CMOS Radiation Performance

No abstract availabl

SEU Analysis of Complex Circuits Implemented in Actel RTAX-S FPGA Devices

No abstract availabl

Characterizing SRAM Single Event Upset in Terms of Single and Double Node Charge Collection

A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAM s state is shown to be based upon the resistive path from the p+-sources in the SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are then predicted and compared to recent SRAM test data