HypsIRI On-Board Science Data Processing

Topics include On-board science data processing, on-board image processing, software upset mitigation, on-board data reduction, on-board 'VSWIR" products, HyspIRI demonstration testbed, and processor comparison

Advanced Hybrid On-Board Science Data Processor - SpaceCube 2.0

Topics include an overview of On-board science data processing, software upset mitigation, on-board data reduction, on-board products, HyspIRI demonstration testbed, SpaceCube 2.0 block diagram, and processor comparison

SpaceCube Version 1.5

SpaceCube 1.5 is a high-performance and low-power system in a compact form factor. It is a hybrid processing system consisting of CPU (central processing unit), FPGA (field-programmable gate array), and DSP (digital signal processor) processing elements. The primary processing engine is the Virtex- 5 FX100T FPGA, which has two embedded processors. The SpaceCube 1.5 System was a bridge to the SpaceCube 2.0 and SpaceCube 2.0 Mini processing systems. The SpaceCube 1.5 system was the primary avionics in the successful SMART (Small Rocket/Spacecraft Technology) Sounding Rocket mission that was launched in the summer of 2011. For SMART and similar missions, an avionics processor is required that is reconfigurable, has high processing capability, has multi-gigabit interfaces, is low power, and comes in a rugged/compact form factor. The original SpaceCube 1.0 met a number of the criteria, but did not possess the multi-gigabit interfaces that were required and is a higher-cost system. The SpaceCube 1.5 was designed with those mission requirements in mind. The SpaceCube 1.5 features one Xilinx Virtex-5 FX100T FPGA and has excellent size, weight, and power characteristics [443 in. (approx. = 10108 cm), 3 lb (approx. = 1.4 kg), and 5 to 15 W depending on the application]. The estimated computing power of the two PowerPC 440s in the Virtex-5 FPGA is 1100 DMIPS each. The SpaceCube 1.5 includes two Gigabit Ethernet (1 Gbps) interfaces as well as two SATA-I/II interfaces (1.5 to 3.0 Gbps) for recording to data drives. The SpaceCube 1.5 also features DDR2 SDRAM (double data rate synchronous dynamic random access memory); 4- Gbit Flash for storing application code for the CPU, FPGA, and DSP processing elements; and a Xilinx Platform Flash XL to store FPGA configuration files or application code. The system also incorporates a 12 bit analog to digital converter with the ability to read 32 discrete analog sensor inputs. The SpaceCube 1.5 design also has a built-in accelerometer. In addition, the system has 12 receive and transmit RS- 422 interfaces for legacy support. The SpaceCube 1.5 processor card represents the first NASA Goddard design in a compact form factor featuring the Xilinx Virtex- 5. The SpaceCube 1.5 incorporates backward compatibility with the Space- Cube 1.0 form factor and stackable architecture. It also makes use of low-cost commercial parts, but is designed for operation in harsh environments

SpaceCube Demonstration Platform

A document discusses how the HST SM4 SpaceCube flight spare was modified to create an experiment called the Space- Cube Demonstration Platform (SC DP) for use on the MISSE7 Space Station payload (in collaboration with NRL). It is designed to serve as an on-orbit platform for demonstrating advanced fault tolerance technologies. A simple C&DH (command and data handling) system was developed for the Virtex4 FPGAs (field programmable gate arrays). Both Virtex4s on each SpaceCube run the same program, and both receive incoming telemetry. The rad-hard service FPGA performs simple error checking to verify that the incoming telemetry is valid. The SpaceCube framework was modified to allow for new program files to be sent from the ground, to be stored on the SpaceCube, and to be executed through ground commands. Each SpaceCube Virtex4 FPGA has resources set aside for experiments that are functionally isolated from the C&DH system. The experiments communicate to the C&DH system through a set of dual port memories, and this area is where the fault-tolerance experiments are executed. With the use of Xilinx commercial Virtex4 FX60 FPGAs, the fault tolerant framework allows the system to recover from radiation upsets that occur in the rad-soft parts (Virtex4 FPGA logic, embedded PPCs in Virtex4 FPGAs, SDRAM and Flash), the C&DH system that runs simultaneously on both Virtex4 FPGAs that uses a robust telemetry packet structure, checksums, and the rad-hard service FPGA to validate incoming telemetry. The ability to be reconfigured from the ground while in orbit is a novel benefit, as well as is the onboard compression capabilities that allow compressed files from the ground to be uploaded to the SpaceCube

SSIVP: Spacecraft Supercomputing Experiment for STP-H6

The Department of Defense Space Test Program (STP) provides spaceflight opportunities for conducting on-orbit research and technology demonstrations to advance the future of spacecraft. STP-H6, the next mission of the program to the International Space Station (ISS), will include a prototype spacecraft supercomputing experiment and framework, called Spacecraft Supercomputing for Image and Video Processing (SSIVP), developed at the National Science Foundation (NSF) Center for High-Performance Reconfigurable Computing (CHREC) at the University of Pittsburgh. SSIVP introduces scalable, high-performance computing (HPC) principles to a CubeSat form-factor to advance the state of the art in space computing. SSIVP adopts the CHREC Space Processor (CSP) concept, a multifaceted design philosophy for a hybrid system of commercial and radiation-hardened (rad-hard) components supplemented with fault-tolerant computing, and a hybrid processor combining fixed-logic CPU and reconfigurable-logic FPGA. SSIVP features five flight-qualified CSPv1 computers as compute nodes, to facilitate this supercomputing concept, and one μCSP smart module, for running a Gallium Nitride (GaN)-based power converter sub-experiment. SSIVP is a versatile, heterogenous platform capable of processing application workloads in the processor or on runtime-reconfigurable FPGA accelerators. In this paper, we present the flight hardware and software, frameworks for parallel and dependable computing, and mission objectives for SSIVP

CSP Hybrid Space Computing for STP-H5/ISEM on ISS

The Space Test Program (STP) at the Department of Defense (DoD) supports the development, evaluation, and advancement of new technologies needed for the future of spaceflight. STP-Houston provides opportunities for DoD and civilian space agencies to perform on-orbit research and technology demonstrations from the International Space Station (ISS). The STP-H5/ISEM (STP-Houston 5, ISS SpaceCube Experiment Mini) payload is scheduled for launch on the upcoming SpaceX 10 mission and will feature new technologies, including a hybrid space computer developed by the NSF CHREC Center, working closely with the NASA SpaceCube Team, known as the CHREC Space Processor (CSP). In this paper, we present the novel concepts behind CSP and the CSPv1 flight technologies on the ISEM mission. The ISEM-CSP system was subjected to environmental testing, including a thermal vacuum test, a vibration test, and two radiation tests, and results were encouraging and are presented. Primary objectives for ISEM-CSP are highlighted, which include processing, compression, and downlink of terrestrial-scene images for display on Earth, and monitoring of upset rates in various subsystems to provide environmental information for future missions. Secondary objectives are also presented, including experiments with features for fault-tolerant computing, reliable middleware services, FPGA partial reconfiguration, device virtualization, and dynamic synthesis

NASA GSFC Development of the SpaceCube MINI

NASA, Goddard Space Flight Center is developing a radiation tolerant miniaturized space processor for use in a multitude of different space flight applications, from free flyers through embedded computing nodes. The Goddard design is building off of our expertise in the hardware/software design of the legacy SpaceCube 1 that flew on the Hubble Servicing Mission and the ISS MISSE7 experiment. The new design will physically conform to the volume requirements of a standard 1U (10cm x 10cm x 10cm) Cubesat. It will incorporate the Xilinx Virtex-5, the latest in high speed, high density, and with the SIRF variant, radiation tolerant FPGA design. Built in peripherals will include 512Mx16 of SDRAM, 96 gigabits of FLASH memory, a radiation hard Aeroflex FPGA (as a watchdog, configuration manager, and scrubber), a 12 bit analog to digital converter, and local power regulation. External interfaces are varied and plentiful with 2 SATA interfaces, 1 Xilinx MGT Interface, 4 Spacewire or 8 LVDS interfaces, 8 RS422 interfaces, and a handful of analog / single ended I/O. Power consumption will range from 5 to 15 watts. The GSFC SpaceCube MINI design even includes one expansion slot to add in an optional user I/O card. With this capability the end user can add in mission unique interfaces without having to resort to using another physical enclosure. The SpaceCube MINI has been designed to use either the radiation tolerant SIRF part from Xilinx, or a regular commercial Xilinx V5. This allows for varied mission requirements to be covered where either computing power and cost or radiation performance can be optimized using the same SpaceCube MINI design. Finally the SpaceCube MINI is designed to allow multiple SpaceCube MINI’s to be daisy chained together, through Gigabit interfaces, enabling it to form an extremely powerful distributed computing node

μCSP: A Diminutive, Hybrid, Space Processor for Smart Modules and CubeSats

The nature of on-board, satellite computing systems is evolving, from centralized to distributed systems, so as to reap benefits in performance, scalability, configurability, and dependability. These distributed systems will feature space computers and smart modules (e.g., smart instruments, smart actuators), each with capability for networking and processing. To address processing and networking needs of future smart modules, as well as improve computing capability for lower-end CubeSats, we developed a new system known as μCSP. Like its more powerful counterpart, the CSPv1, μCSP is designed with a hybrid mix of commercial and radiation-hardened components supplemented with mechanisms from fault-tolerant computing. μCSP also features a hybrid processor architecture, with a mix of fixed and reconfigurable logic, but all in a smaller form factor with lower SWaP-C. μCSP is smaller than a credit card and designed to integrate into (but not be limited to) 1U SmallSat form factors. Research showcased in this paper also includes an overview of our concepts for smart modules in distributed computing systems for space, both within a single spacecraft and across multiple spacecraft, in terms of a framework for the construction of a variety of reusable, modular 1U boards with varying functionality for enhanced satellite capability and configuration

HIV is associated with endothelial activation despite ART, in a sub-Saharan African setting

Objective To study the relationship between endothelial dysfunction, HIV infection, and stroke in Malawians. Methods Using a cross-sectional design, we measured plasma levels of intercellular adhesion molecule-1 (ICAM-1), plasminogen activator inhibitor-1 (PAI-1), vascular endothelial growth factor (VEGF), and soluble thrombomodulin (sTM) in stroke patients and controls, stratified by HIV status. These biomarkers were measured using ELISA. After dichotomization, each biomarker was used as the dependent variable in a multivariable logistic regression model. Primary independent variables included HIV and stroke status. Adjustment variables were age, sex, hypertension, diabetes mellitus, tobacco and alcohol consumption, personal/family history of stroke, antiretroviral therapy status, and hypercholesterolemia. Results Sixty-one stroke cases (19 HIV+) and 168 controls (32 HIV+) were enrolled. The median age was 55 years (38.5-65.0) for controls and 52 years (38.0-73.0) for cases ( = 0.38). The median CD4 T-cell count was 260.1 cells/mm (156.3-363.9) and 452 cells/mm (378.1-527.4) in HIV-infected cases and controls, respectively. HIV infection was independently associated with high levels of ICAM-1 (OR = 3.6, 95% CI: 1.3-10.6, = 0.018) in controls but not in stroke cases even after excluding patients with a viral load >1,000 RNA copies/mL (OR = 4.1, 95% CI: 1.3-13.1, = 0.017). There was no association between the clinical profiles of HIV-positive controls or HIV-positive stroke and high levels of PAI-1, VEGF, and sTM. Conclusions HIV infection is associated with endothelial activation despite antiretroviral treatment. Our findings underscore the need for larger clinical cohorts to better understand the contribution of this perturbation of the endothelial function to the increasing burden of cardiovascular diseases in sub-Saharan Africa