Comprehensive investigation of Ge-Si bonded interfaces using oxygen radical activation

In this work, we investigate the directly bonded germanium-silicon interfaces to facilitate the development of high quality germanium silicon hetero integration at the wafer scale. X-ray photoelectron spectroscopy data is presented which provides the chemical composition of the germanium surfaces as a function of the hydrophilic bonding reaction at the interface. The bonding process induced long range deformation is detected by synchrotron x-ray topography. The hetero-interface is characterized by measuring forward and reverse current, and by high resolution transmission electron microscopy. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3601355

Improvement of carrier ballisticity in junctionless nanowire transistors

In this work we show that junctionless nanowire transistor (JNT) exhibits lower degree of ballisticity in subthreshold and higher ballisticity above threshold compare to conventional inversion-mode transistors, according to quantum mechanical simulations. The lower degradation of the ballisticity above threshold region gives the JNT near-ballistic transport performance and hence a high current drive. On the other hand, lower ballisticity in subthreshold region helps reducing the off-current and improves the subthreshold slope. A three-dimensional quantum mechanical device simulator based on the nonequilibrium Green's function formalism in the uncoupled mode-space approach has been developed to extract the physical parameters of the devices. (C) 2011 American Institute of Physics. (doi:10.1063/1.3559625

Low temperature exfoliation process in hydrogen-implanted germanium layers

The feasibility of transferring hydrogen-implanted germanium to silicon with a reduced thermal budget is demonstrated. Germanium samples were implanted with a splitting dose of 5 x 10(16) H(2)(+) cm(-2) at 180 keV and a two-step anneal was performed. Surface roughness and x-ray diffraction pattern measurements, combined with cross-sectional TEM analysis of hydrogen-implanted germanium samples were carried out in order to understand the exfoliation mechanism as a function of the thermal budget. It is shown that the first anneal performed at low temperature (<= 150 degrees C for 22 h) enhances the nucleation of hydrogen platelets significantly. The second anneal is performed at 300 degrees C for 5 min and is shown to complete the exfoliation process by triggering the formation of extended platelets. Two key results are highlighted: (i) in a reduced thermal budget approach, the transfer of hydrogen-implanted germanium is found to follow a mechanism similar to the transfer of hydrogen-implanted InP and GaAs, (ii) such a low thermal budget (<300 degrees C) is found to be suitable for directly bonded heterogeneous substrates, such as germanium bonded to silicon, where different thermal expansion coefficients are involved. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3326942

Characterization of a junctionless diode

A diode has been realised using a silicon junctionless (JL) transistor. The device contains neither PN junction nor Schottky junction. The device is measured at different temperatures. The characteristics of the JL diode are essentially identical to those of a regular PN junction diode. The JL diode has an on/off current ratio of 10(8), an ideality factor of 1.09, and a reverse leakage current of 1 x 10(-14) A at room temperature. The mechanism of the leakage current is discussed using the activation energy (E-A). The turn-on voltage of the device can be tuned by JL transistor threshold voltage. (C) 2011 American Institute of Physics. (doi: 10.1063/1.3608150

Random telegraph-signal noise in junctionless transistors

Random telegraph-signal noise (RTN) is measured in junctionless metal-oxide-silicon field-effect transistors (JL MOSFETs) as a function of gate and drain voltage and temperature. It is shown that the RTN in JL MOSFETs increases significantly when an accumulation layer is formed. The amplitude of RTN is considerably smaller in JL devices than in inversion-mode MOSFET fabricated using similar fabrication parameters. A measurement technique is developed to extract the main parameters of the traps, including the average charge capture and emission time from the traps. (C) 2011 American Institute of Physics. (doi:10.1063/1.3557505

Field-effect mobility extraction in nanowire field-effect transistors by combination of transfer characteristics and random telegraph noise measurements

A technique based on the combined measurements of random telegraph-signal noise amplitude and drain current vs. gate voltage characteristics is proposed to extract the channel mobility in inversion-mode and accumulation-mode nanowire transistors. This method does not require the preliminary knowledge of the gate oxide capacitance or that of the channel width. The method accounts for the presence of parasitic source and drain resistance effect. It has been used to extract the zero-field mobility and the field mobility reduction factor in inversion-mode and junctionless transistors operating in accumulation mode. (C) 2011 American Institute of Physics. (doi:10.1063/1.3626038

Reduced electric field in junctionless transistors

The electric field perpendicular to the current flow is found to be significantly lower in junctionless transistors than in regular inversion-mode or accumulation-mode field-effect transistors. Since inversion channel mobility in metal-oxide-semionductor transistors is reduced by this electric field, the low field in junctionless transistor may give them an advantage in terms of current drive for nanometer-scale complementary metal-oxide semiconductor applications. This observation still applies when quantum confinement is present. (C) 2010 American Institute of Physics. (doi:10.1063/1.3299014

Fabrication and Characterization of SOI Multi Gate Field Effect Transistors with High-K Dielectrics and Metal Gates (Fabricatie en karakterisatie van SOI multiple gate veldeffecttransistoren met high-k poortdielectrica en metaalpoorten)

Er wordt een voortdurende inspanning geleverd om de afmetingen van transistoren te verkleinen en zo hun integratiedichtheid te verbeteren. Hierbij is het belangrijk dat de productiekosten zo laag mogelijk blijven. Echter, door deze verkleining zijn sommige parasitaire effecten dominant geworden en de performantie verbetering ligt dan ook lager dan wat verwacht wordt. In deze thesis zullen twee problemen, inherent aan de transistorverkleining, besproken worden: het gebruik van zeer korte kanalen brengt een verlies aan elektrostatische controle van de poortelektrode over de inversielaag in het kanaal met zich mee. Dit wordt ook 'Drain Induced Barrier Lowering' genoemd en leidt tot het 'Korte Kanaal Effect' (KKE). Daarnaast bereikt de dikte van het poortdiëlektricum stilaan de limiet van enkele atoomlagen en dit veroorzaakt een dramatische toename in de tunnel lekstroom. In deze context kunnen nieuwe architecturen zoals de 'Multiple-Gate FET' (MuGFET) helpen om de strenge eisen die gesteldworden aan de dikte van high-k diëlektrica te verlichten. In deze transistoren kan een betere elektrostatische controle verkregen worden door een dun silicium kanaal te omsluiten door twee of meer poortelektrodes. Een significante reductie van het KKE kan bereikt worden door het verminderen van de afstand tussen de poortelektrodes (d.w.z. door het verdunnen van de silicium film). Op deze manier is een aanzienlijke verdunning van het poortdiëlektricum niet meer nodig. Dit proefschrift behandelt de fabricatievan poortelektroden met high-k diëlektrica en metaal en de karakterisering ervan in fully depleted triple-gate FETs, gemaakt in Silicon-On-Insulator (SOI) substraten. Het doel is om te bepalen in welke mate de integratie van deze poortelektroden een impact kan hebben op de werkfunctie van triple-gate FETs. Voor de werkfunctie extractie werd een nieuwe methode ontwikkeld, welke in staat is om gelijktijdig rekening te houden met de aanwezigheid van high-k diëlektrica en het ontbreken van een substraatcontact, typisch voor SOI transistoren. Hiervoor werd aangetoond dat de afhankelijkheid van de MOSFET bandenstructuur en de tunnel lekstroom universeel is. Daarnaast werden verschillende methoden voorgesteld en geanalyseerd om de werkfunctie in triple-gate FETs te controleren en af te stellen. In een laatste deel werden de gevolgen bestudeerd van de spanning, veroorzaakt door de poortelektrode, op de prestaties van een geïsoleerde triple-gate FET.status: publishe

Investigation of Ionic Conductivity in Track-etched Nanoporous Polyimide Membranes using a Microwave Technique

The in situ characterization of membranes for fuel cell applications is a rather complex and time-consuming procedure. It is therefore interesting to develop simple, short, and reproducible characterization tests and to limit in situ measurement only to the most promising materials. In this paper, a new characterization method is proposed to extract the DC ionic conductivity of track-etched nanoporous polyimide membranes from microwave measurements

Strain characterization of directly bonded germanium-to-silicon substrates

Synchrotron X-Ray Topography (SXRT) has been performed on a germanium-silicon substrate fabricated by direct wafer bonding. SXRT allows for quantification of the stress at the bonded interface. This non-invasive techniques help assess the likelihood of defect nucleation induced by the bonding process. This study shows that the stress at the bonded interface is an order of magnitude lower than the level required to cause spontaneous nucleation of threading dislocations.</jats:p