Homogeneous and heterogeneous MPSoC architectures with network-on-chip connectivity for low-power and real-time multimedia signal processing

Two multiprocessor system-on-chip (MPSoC) architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC) infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices

Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

A VLSI macrocell for edge-preserving video noise reduction is proposed in the paper. It is based on a nonlinear rational filter enhanced by a noise estimator for blind and dynamic adaptation of the filtering parameters to the input signal statistics. The VLSI filter features a modular architecture allowing the extension of both mask size and filtering directions. Both spatial and spatiotemporal algorithms are supported. Simulation results with monochrome test videos prove its efficiency for many noise distributions with PSNR improvements up to 3.8 dB with respect to a nonadaptive solution. The VLSI macrocell has been realized in a 0.18 m CMOS technology using a standard-cells library; it allows for real-time processing of main video formats, up to 30 fps (frames per second) 4CIF, with a power consumption in the order of few mW

A cost-effective 10-bit D/A converter for digital-input MOEMS micromirror actuation

The design of a 10-bit resistor-string digital-to-analog converter (DAC) for MOEMS micromirror interfacing is addressed in this paper. The proposed DAC, realized in a 0.18-μm BCD technology, features a folded resistor-string stage with a switch matrix and address decoders plus an output voltage buffer stage. The proposed DAC and buffer circuitry are key elements of an innovative scanning micromirror actuator, characterized by direct digital input, full differential driving, and linear response. With respect to the the state-of-the-art resistor-string converters in similar technologies, the proposed DAC has comparable nonlinearity (INL, DNL) performances while it has the advantage of a smaller area occupation, 0.17 mm2, including output buffer, and relatively low-power consumption, 200 μW at 500 kSPS and few μW in idle mode

Fixed-point MAP decoding of channel codes

This paper describes the fixed-point model of the maximum a posteriori (MAP) decoding algorithm of turbo and low-density parity-check (LDPC) codes, the most advanced channel codes adopted by modern communication systems for forward error correction (FEC). Fixed-point models of the decoding algorithms are developed in a unified framework based on the use of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. This approach aims at bridging the gap toward the design of a universal, multistandard decoder of channel codes, capable of supporting the two classes of codes and having reduced requirements in terms of silicon area and power consumption and so suitable to mobile applications. The developed models allow the identification of key parameters such as dynamic range and number of bits, whose impact on the error correction performance of the algorithm is of pivotal importance for the definition of the architectural tradeoffs between complexity and performance. This is done by taking the turbo and LDPC codes of two recent communication standards such asWiMAX and 3GPP-LTE as a reference benchmark for a mobile scenario and by analyzing their performance over additive white Gaussian noise (AWGN) channel for different values of the fixed-point parameters

Crypto accelerators for power-efficient and realtime on-chip implementation of secure algorithms

The demand for data exchange is ever growing. Internet of Things (IoT), industry 4.0, smart city and next-generation interconnected vehicles are some examples of scenarios in which a high volume of nodes share data across networks. Hence, the data protection plays a fundamental aspect to avoid disclosure or manipulation of sensitive information and disruption of services, particularly in safety critical applications. On the other hand, also the compute power at disposal of possible attackers and hackers is growing, and next-future post-quantum capabilities will require the usage of longer keys, certificates and digital signatures, to preserve the security level offered by cryptographic functions. This will affect not only the amount of exchange data, but also the computational resources to secure data, increasing processing time, latencies and power consumption, and lowering data rates. In this work, we investigate different implementation strategies to overcome such performance limitations. This work provides a comparison among pure software approach (both on 32b and 64b processors) and hardware-based solutions we developed for FPGA and ASIC System-on-Chip platforms, for the most common symmetric-key and public-key cryptographic algorithms. The proposed hardware accelerators feature one order of magnitude higher throughput (and lower latency) and more than two orders lower power consumption than their software counterparts. A highly configurable cryptographic suite is proposed that can be customized according to the application requirements and thus able to increase as much as possible the efficiency in terms of energy per enciphered bits per secon

Wireless Sensing Based on RFID and Capacitive Technologies for Safety in Marble Industry Process Control

This paper presents wireless sensing systems to increase safety and robustness in industrial process control, particularly in industrial machines for marble slab working. The process is performed by abrasive or cutting heads activated independently by the machine controller when the slab, transported on a conveyer belt, is under them. Current slab detection systems are based on electromechanical or optical devices at the machine entrance stage, suffering from deterioration and from the harsh environment. Slab displacement or break inside the machine due to the working stress may result in safety issues and damages to the conveyer belt due to incorrect driving of the working tools. The experimented contactless sensing techniques are based on four RFID and two capacitive sensing technologies and on customized hardware/software. The proposed solutions aim at overcoming some limitations of current state-of-the-art detection systems, allowing for reliable slab detection, outside and/or inside the machine, while maintaining low complexity and at the same time robustness to industrial harsh conditions. The proposed sensing devices may implement a wireless or wired sensor network feeding detection data to the machine controller. Data integrity check and process control algorithms have to be implemented for the safety and reliability of the overall industrial process

Stretched-Wire Techniques and Measurements for the Alignment of a 15GHz RF-BPM for CLIC

For the Compact LInear Collider (CLIC) project at CERN, maintaining low emittance beams, as they are transported along the two independent 10-20 km long main linacs, is crucial. The beam trajectory therefore has to be very well aligned to the magnetic centre of the quadrupole magnets. A series of microwave cavity beam position monitors (BPM) is foreseen to detect the position of the beam along the main linacs to precisely monitor the beam trajectory in the circular beam pipe of only 8 mm diameter. The PACMAN project aims to demonstrate the pre-alignment of the magnetic field of a main CLIC quadrupole with the electro-magnetic centre of a 15 GHz RF-BPM to the required sub-micron accuracy. This paper focuses on stretched-wire measurements of a CLIC Test Facility (CTF) cavity BPM, to locate its electrical centre. Details of two measurement methods are discussed: RF signal excitation of the wire and analysis of RF signal transfer through the slot-coupled waveguides of the cavity, using the stretched wire as a passive target. This contribution will present the theory behind these measurements, their electromagnetic analysis and first, preliminary experimental results

Trading-Off Machine Learning Algorithms towards Data-Driven Administrative-Socio-Economic Population Health Management

Together with population ageing, the number of people suffering from multimorbidity is increasing, up to more than half of the population by 2035. This part of the population is composed by the highest-risk patients, who are, at the same time, the major users of the healthcare systems. The early identification of this sub-population can really help to improve people’s quality of life and reduce healthcare costs. In this paper, we describe a population health management tool based on state-of-the-art intelligent algorithms, starting from administrative and socio-economic data, for the early identification of high-risk patients. The study refers to the population of the Local Health Unit of Central Tuscany in 2015, which amounts to 1,670,129 residents. After a trade-off on machine learning models and on input data, Random Forest applied to 1-year of historical data achieves the best results, outperforming state-of-the-art models. The most important variables for this model, in terms of mean minimal depth, accuracy decrease and Gini decrease, result to be age and some group of drugs, such as high-ceiling diuretics. Thanks to the low inference time and reduced memory usage, the resulting model allows for real-time risk prediction updates whenever new data become available, giving General Practitioners the possibility to early adopt personalised medicine

Testing of DC/DC converters for 48 V electric vehicles

DC/DC applications in automotive market are expected to require new system specifications in next years. Because of the spreading of electrical cars, the power line at 48V will be very common. Moreover, the converter chips and external passives are required to occupy less area. A DC/DC solution, meeting such requirements, is presented in this work. The switched capacitors architecture is intended to reduce external passive devices space occupation, whereas sustained electrical power is kept high. This paper discusses a preliminary version of the converter, with experimental results from measurements, and presents the final chip architecture, with some simulation result data