A programmable BIST architecture for clusters of Multiple-Port SRAMs

This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timin

Single-Event Upset Analysis and Protection in High Speed Circuits

The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a single event upset (SEU) caused by particle strike on the internal nodes of a flip-flo

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC

This paper proposes an analytical method to assess the soft-error rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML (Unified Modeling Language) model of the SoC and the raw soft- error rate of different parts of the platform as its inputs. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. The Dynamic behavior of each core is used to determine the propagation probability of each variable disturbance to the core outputs. Furthermore, the SER and the execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the So

Strongly correlated double Dirac fermions

Double Dirac fermions have recently been identified as possible quasiparticles hosted by three-dimensional crystals with particular non-symmorphic point group symmetries. Applying a combined approach of ab-initio methods and dynamical mean field theory, we investigate how interactions and double Dirac band topology conspire to form the electronic quantum state of Bi$_2$CuO$_4$. We derive a downfolded eight-band model of the pristine material at low energies around the Fermi level. By tuning the model parameters from the free band structure to the realistic strongly correlated regime, we find a persistence of the double Dirac dispersion until its constituting time reveral symmetry is broken due to the onset of magnetic ordering at the Mott transition. We analyze pressure as a promising route to realize a double-Dirac metal in Bi$_2$CuO$_4$

Online and Offline BIST in IP-Core Design

This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraint

Protocol for electrophysiological monitoring of carotid endarterectomies.

Near zero stroke rates can be achieved in carotid endarterectomy (CEA) surgery with selective shunting and electrophysiological neuromonitoring. though false negative rates as high as 40% have been reported. We sought to determine if improved training for interpretation of the monitoring signals can advance the efficacy of selective shunting with electrophysiological monitoring across multiple centers, and determine if other factors could contribute to the differences in reports. Processed and raw beta band (12.5-30 Hz) electroencephalogram (EEG) and median and tibial nerve somatosensory evoked potentials (SSEP) were monitored in 668 CEA cases at six surgical centers. A decrease in amplitude of 50% or more in any EEG or SSEP channel was the criteria for shunting or initiating a neuroprotective protocol. A reduction of 50% or greater in the beta band of the EEG or amplitude of the SSEP was observed in 150 cases. No patient showed signs of a cerebral infarct after surgery. Selective shunting based on EEG and SSEP monitoring can reduce CEA intraoperative stroke rate to a near zero level if trained personnel adopted standardized protocols. We also found that the rapid administration of a protective stroke protocol by attending anesthesiologists was an important aspect of this success rate

EChO Payload electronics architecture and SW design

EChO is a three-modules (VNIR, SWIR, MWIR), highly integrated spectrometer, covering the wavelength range from 0.55 $\mu$m, to 11.0 $\mu$m. The baseline design includes the goal wavelength extension to 0.4 $\mu$m while an optional LWIR module extends the range to the goal wavelength of 16.0 $\mu$m. An Instrument Control Unit (ICU) is foreseen as the main electronic subsystem interfacing the spacecraft and collecting data from all the payload spectrometers modules. ICU is in charge of two main tasks: the overall payload control (Instrument Control Function) and the housekeepings and scientific data digital processing (Data Processing Function), including the lossless compression prior to store the science data to the Solid State Mass Memory of the Spacecraft. These two main tasks are accomplished thanks to the Payload On Board Software (P-OBSW) running on the ICU CPUs.Comment: Experimental Astronomy - EChO Special Issue 201

A note on Poisson goodness-of-fit tests for ionizing radiation induced chromosomal aberration samples

Purpose: To present Poisson exact goodness-of-fit tests as alternatives and complements to the asymptotic u-test, which is the most widely used in cytogenetic biodosimetry, to decide whether a sample of chromosomal aberrations in blood cells comes from an homogeneous or inhomogeneous exposure. Materials and methods: Three Poisson exact goodness-of-fit test from the literature are introduced and implemented in the R environment. A Shiny R Studio application, named GOF Poisson, has been updated for the purpose of giving support to this work. The three exact tests and the u-test are applied in chromosomal aberration data from clinical and accidental radiation exposure patients. Results: It is observed how the u-test is not an appropriate approximation in small samples with small yield of chromosomal aberrations. Tools are provided to compute the three exact tests, which is not as trivial as the implementation of the u-test. Conclusions: Poisson exact goodness-of-fit tests should be considered jointly to the u-test for detecting inhomogeneous exposures in the cytogenetic biodosimetry practice

Interactive Educational Tool for Memory Testing

Memories are one of the most important components in digital systems like SoCs. The high density of their cell array makes memories extremely vulnerable to physical defects. Hence, memory testing and Design-for-Test became one of the crucial tasks in the design of complex and heterogeneous SoCs. Politecnico di Torino and the Institute of Informatics have a wide experience in the field of RAM testing (i.e., automatic march test generation, fault simulators, memory BIST generators etc.). This work is a tentative to put the joint experience of our research groups in developing an interactive educational tool for the students that should introduce standard and well-known methods of memory testing based on BIST. The MemBIST Java Applet and the March Test Generator were two individual tools designed and implemented at the two mentioned institutions. They were merged into one tool in order to facilitate its usage also by the professional