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A programmable BIST architecture for clusters of Multiple-Port SRAMs

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Publication date
1 January 2000
Publisher
IEEE
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    Abstract

    This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timin

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