Hardware calibrated learning to compensate heterogeneity in analog RRAM-based Spiking Neural Networks

Spiking Neural Networks (SNNs) can unleash the full power of analog Resistive Random Access Memories (RRAMs) based circuits for low power signal processing. Their inherent computational sparsity naturally results in energy efficiency benefits. The main challenge implementing robust SNNs is the intrinsic variability (heterogeneity) of both analog CMOS circuits and RRAM technology. In this work, we assessed the performance and variability of RRAM-based neuromorphic circuits that were designed and fabricated using a 130 nm technology node. Based on these results, we propose a Neuromorphic Hardware Calibrated (NHC) SNN, where the learning circuits are calibrated on the measured data. We show that by taking into account the measured heterogeneity characteristics in the off-chip learning phase, the NHC SNN self-corrects its hardware non-idealities and learns to solve benchmark tasks with high accuracy. This work demonstrates how to cope with the heterogeneity of neurons and synapses for increasing classification accuracy in temporal tasks

Utilisation of an operative difficulty grading scale for laparoscopic cholecystectomy

Background A reliable system for grading operative difficulty of laparoscopic cholecystectomy would standardise description of findings and reporting of outcomes. The aim of this study was to validate a difficulty grading system (Nassar scale), testing its applicability and consistency in two large prospective datasets. Methods Patient and disease-related variables and 30-day outcomes were identified in two prospective cholecystectomy databases: the multi-centre prospective cohort of 8820 patients from the recent CholeS Study and the single-surgeon series containing 4089 patients. Operative data and patient outcomes were correlated with Nassar operative difficultly scale, using Kendall’s tau for dichotomous variables, or Jonckheere–Terpstra tests for continuous variables. A ROC curve analysis was performed, to quantify the predictive accuracy of the scale for each outcome, with continuous outcomes dichotomised, prior to analysis. Results A higher operative difficulty grade was consistently associated with worse outcomes for the patients in both the reference and CholeS cohorts. The median length of stay increased from 0 to 4 days, and the 30-day complication rate from 7.6 to 24.4% as the difficulty grade increased from 1 to 4/5 (both p < 0.001). In the CholeS cohort, a higher difficulty grade was found to be most strongly associated with conversion to open and 30-day mortality (AUROC = 0.903, 0.822, respectively). On multivariable analysis, the Nassar operative difficultly scale was found to be a significant independent predictor of operative duration, conversion to open surgery, 30-day complications and 30-day reintervention (all p < 0.001). Conclusion We have shown that an operative difficulty scale can standardise the description of operative findings by multiple grades of surgeons to facilitate audit, training assessment and research. It provides a tool for reporting operative findings, disease severity and technical difficulty and can be utilised in future research to reliably compare outcomes according to case mix and intra-operative difficulty

Population‐based cohort study of outcomes following cholecystectomy for benign gallbladder diseases

Background The aim was to describe the management of benign gallbladder disease and identify characteristics associated with all‐cause 30‐day readmissions and complications in a prospective population‐based cohort. Methods Data were collected on consecutive patients undergoing cholecystectomy in acute UK and Irish hospitals between 1 March and 1 May 2014. Potential explanatory variables influencing all‐cause 30‐day readmissions and complications were analysed by means of multilevel, multivariable logistic regression modelling using a two‐level hierarchical structure with patients (level 1) nested within hospitals (level 2). Results Data were collected on 8909 patients undergoing cholecystectomy from 167 hospitals. Some 1451 cholecystectomies (16·3 per cent) were performed as an emergency, 4165 (46·8 per cent) as elective operations, and 3293 patients (37·0 per cent) had had at least one previous emergency admission, but had surgery on a delayed basis. The readmission and complication rates at 30 days were 7·1 per cent (633 of 8909) and 10·8 per cent (962 of 8909) respectively. Both readmissions and complications were independently associated with increasing ASA fitness grade, duration of surgery, and increasing numbers of emergency admissions with gallbladder disease before cholecystectomy. No identifiable hospital characteristics were linked to readmissions and complications. Conclusion Readmissions and complications following cholecystectomy are common and associated with patient and disease characteristics

The development and validation of a scoring tool to predict the operative duration of elective laparoscopic cholecystectomy

Background: The ability to accurately predict operative duration has the potential to optimise theatre efficiency and utilisation, thus reducing costs and increasing staff and patient satisfaction. With laparoscopic cholecystectomy being one of the most commonly performed procedures worldwide, a tool to predict operative duration could be extremely beneficial to healthcare organisations. Methods: Data collected from the CholeS study on patients undergoing cholecystectomy in UK and Irish hospitals between 04/2014 and 05/2014 were used to study operative duration. A multivariable binary logistic regression model was produced in order to identify significant independent predictors of long (> 90 min) operations. The resulting model was converted to a risk score, which was subsequently validated on second cohort of patients using ROC curves. Results: After exclusions, data were available for 7227 patients in the derivation (CholeS) cohort. The median operative duration was 60 min (interquartile range 45–85), with 17.7% of operations lasting longer than 90 min. Ten factors were found to be significant independent predictors of operative durations > 90 min, including ASA, age, previous surgical admissions, BMI, gallbladder wall thickness and CBD diameter. A risk score was then produced from these factors, and applied to a cohort of 2405 patients from a tertiary centre for external validation. This returned an area under the ROC curve of 0.708 (SE = 0.013, p  90 min increasing more than eightfold from 5.1 to 41.8% in the extremes of the score. Conclusion: The scoring tool produced in this study was found to be significantly predictive of long operative durations on validation in an external cohort. As such, the tool may have the potential to enable organisations to better organise theatre lists and deliver greater efficiencies in care

The Cholecystectomy As A Day Case (CAAD) Score: A Validated Score of Preoperative Predictors of Successful Day-Case Cholecystectomy Using the CholeS Data Set

Background Day-case surgery is associated with significant patient and cost benefits. However, only 43% of cholecystectomy patients are discharged home the same day. One hypothesis is day-case cholecystectomy rates, defined as patients discharged the same day as their operation, may be improved by better assessment of patients using standard preoperative variables. Methods Data were extracted from a prospectively collected data set of cholecystectomy patients from 166 UK and Irish hospitals (CholeS). Cholecystectomies performed as elective procedures were divided into main (75%) and validation (25%) data sets. Preoperative predictors were identified, and a risk score of failed day case was devised using multivariate logistic regression. Receiver operating curve analysis was used to validate the score in the validation data set. Results Of the 7426 elective cholecystectomies performed, 49% of these were discharged home the same day. Same-day discharge following cholecystectomy was less likely with older patients (OR 0.18, 95% CI 0.15–0.23), higher ASA scores (OR 0.19, 95% CI 0.15–0.23), complicated cholelithiasis (OR 0.38, 95% CI 0.31 to 0.48), male gender (OR 0.66, 95% CI 0.58–0.74), previous acute gallstone-related admissions (OR 0.54, 95% CI 0.48–0.60) and preoperative endoscopic intervention (OR 0.40, 95% CI 0.34–0.47). The CAAD score was developed using these variables. When applied to the validation subgroup, a CAAD score of ≤5 was associated with 80.8% successful day-case cholecystectomy compared with 19.2% associated with a CAAD score >5 (p < 0.001). Conclusions The CAAD score which utilises data readily available from clinic letters and electronic sources can predict same-day discharges following cholecystectomy

Monolayer Graphene Coupled to a Flexible Plasmonic Nanograting for Ultrasensitive Strain Monitoring

Plasmonically coupled graphene structures have shown great promise for sensing applications. Their complex and cumbersome fabrication, however, has prohibited their widespread application and limited their use to rigid, planar surfaces. Here, a plasmonic sensor based on gold nanowire arrays on an elastomer with an added graphene monolayer is introduced. The stretchable plasmonic nanostructures not only significantly enhance the Raman signal from graphene, but can also be used by themselves as a sensor platform for 2D strain sensing. These nanowire arrays on an elastomer are fabricated by template-stripping based nanotransfer printing, which enables a simple and fast production of stable nanogratings. The ultrasmooth surfaces of such transferred structures facilitate reliable large-area transfers of graphene monolayers. The resulting coupled graphene-nanograting construct exhibits ultrahigh sensitivity to applied strain, which can be detected by shifts in the plasmonic-enhanced Raman spectrum. Furthermore, this sensor enables the detection of adsorbed molecules on nonplanar surfaces through graphene-assisted surface enhanced Raman spectroscopy (SERS). The simple fabrication of the plasmonic nanowire array platform and the graphene-coupled devices have the potential to trigger widespread SERS applications and open up new opportunities for high-sensitivity strain sensing applications

Novel 1T2R1T RRAM-based Ternary Content Addressable Memory for Large Scale Pattern Recognition

International audienceResistive Random Access Memories (RRAMs) are a promising solution to implement Ternary Content Addressable Memories (TCAMs) that are more area-and energy-efficient with respect to Static Random Access Memory (SRAM)-based TCAMs. However, RRAM-based TCAMs are limited in the number of bits per word due to the low ratio between the resistances of the high and low resistance states (HRS/LRS) and resistance variability of RRAM. Such a limitation on the word length hinders the parallel search of a very large number of data bits for data-intensive applications. To overcome this issue, for the first time, we propose a new TCAM cell composed of two transistors and two RRAMs in a 1T2R1T configuration, where a RRAM voltage divider (2R) biases a transistor gate (1T) and an additional transistor is used to program the RRAMs (1T). A 3x128bits 1T2R1T TCAM macro were designed, integrated and extensively characterized. We experimentally demonstrate that the sensing margin of the proposed structure is insensitive to HRS/LRS RRAM resistance ratio and variability. With respect to the most common type of 2T2R RRAM-based TCAM [1-3], the proposed circuit improves the sensing margin by >5000x while reaching search times of 0.93ns. This allows the search of large volumes of data in parallel. In addition, the proposed structure improves programming and search endurance by 100x and >10x, respectively. I. PROPOSED 1T2R1T TCAM CIRCUIT TCAM performs parallel searches by comparing input searched data with data stored in the TCAM and returning the data address when a match occurs [1]. They provide a lookup response in a single clock cycle making them faster and more energy-efficient than random access memory-based search systems. High pattern matching speeds make TCAM a key function for data-intensive applications, such as Internet Protocol (IP) lookup, word search, and routing in neuromorphic circuits [1, 4-5]. Conventional TCAMs based on SRAMs suffer from low area density and static power consumption. Resistive Memory (RRAM)-based TCAMs have been demonstrated [2, 6-10] enabling to overcome these challenges without degrading performance (search energy and time) (Fig.1). The most common RRAM-based TCAM is composed of two pairs of access transistors and RRAMs (2T2R) connected in parallel on a Match Line (ML) [1-3]. However, these structures are constrained in word length due to the low ON/OFF current ratio (10) is required to enable parallel searches of longer words. Here we propose a new TCAM cell composed of two transistors and two RRAMs in a 1T2R1T configuration (Fig.2a), in which two RRAMs (2R) compose a voltage divider that biases the transistor gate of N2 (1T) for search operations. An additional transistor N1 (1T) works as an access transistor to program the RRAMs. The searching scheme is shown in Fig.2b. The ML is first pre-charged at VDD (transistors N1 and N2 are OFF). The ML is then left floating and a search voltage V search is applied across the RRAM voltage divider. When the search bit is '1', V search is applied on the top of the voltage divider (SLT), while maintaining SLF to 0V. When the search bit is '0', V search is applied on the bottom (SLF). The internal voltage V INT depends on R X and R Y values. If the stored and searched data match (V INT~0 V) transistor N2 remains OFF and the ML stays high. If we have a mismatch (V INT~Vsearch) N2 turns ON and the ML is pulled down to ground. Fig.3a and b show a photo of the fabricated 3x128bits 1T2R1T RRAM-based TCAM and a SEM cross section of the integrated RRAMs, respectively. HfO 2-based RRAMs are integrated in the Back End of Line of a 130nm CMOS process [11]. During ML sensing, in the most common 2T2R RRAM-based TCAM (Fig.4a), the top electrodes of both RRAMs are connected to the ML. Current flows in the 1T1R branches with the selector transistor in the ON state, discharging the ML. In case of match, the ML slowly discharges through RRAMs in HRS (top) whereas in case of mismatch the ML discharges quickly through RRAMs in LRS (bottom). Since the leakage currents of the TCAM cells on the same ML add together, the limited HRS/LRS resistance ratio makes difficult to distinguish between a match and 1-bit mismatch state (the hardest mismatch to detect) for long TCAM words. In the proposed 1T2R1T structure (Fig.4b), the ML is connected to transistors controlled by the RRAM voltage divider (N2). Therefore, the sensing margin no longer depends on HRS/LRS ratio (~30 at V search =0.6V) but on the MOSFET current ratio (~10 at V search =0.6V as shown on the transistor characteristic in Fig.5), leading to the possibility of longer word search. II. SENSING MARGIN AND SEARCH CAPACITY We performed extensive circuit-level electrical characterization of the fabricated 1T2R1T TCAM array. Measurements are performed on the 128-bits middle TCAM of Fig.3a. The transistor N1 is used to perform Forming, Set and Reset operations using the standard 1T1R scheme. The configuration with both cells in LRS is forbidden (always miss case). The programming sequence of Fig.6 top is adopted in IEDM19-839 35.5.

High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks

International audienc