121 research outputs found

    Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs

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    Low energy digital circuit design using sub-threshold operation

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2006.Includes bibliographical references (p. 189-202).Scaling of process technologies to deep sub-micron dimensions has made power management a significant concern for circuit designers. For emerging low power applications such as distributed micro-sensor networks or medical applications, low energy operation is the primary concern instead of speed, with the eventual goal of harvesting energy from the environment. Sub-threshold operation offers a promising solution for ultra-low-energy applications because it often achieves the minimum energy per operation. While initial explorations into sub-threshold circuits demonstrate its promise, sub-threshold circuit design remains in its infancy. This thesis makes several contributions that make sub-threshold design more accessible to circuit designers. First, a model for energy consumption in sub-threshold provides an analytical solution for the optimum VDD to minimize energy. Fitting this model to a generic circuit allows easy estimation of the impact of processing and environmental parameters on the minimum energy point. Second, analysis of device sizing for sub-threshold circuits shows the trade-offs between sizing for minimum energy and for minimum voltage operation.(cont.) A programmable FIR filter test chip fabricated in 0.18pum bulk CMOS provides measurements to confirm the model and the sizing analysis. Third, a low-overhead method for integrating sub-threshold operation with high performance applications extends dynamic voltage scaling across orders of magnitude of frequency and provides energy scalability down to the minimum energy point. A 90nm bulk CMOS test chip confirms the range of operation for ultra-dynamic voltage scaling. Finally, sub-threshold operation is extended to memories. Analysis of traditional SRAM bitcells and architectures leads to development of a new bitcell for robust sub-threshold SRAM operation. The sub-threshold SRAM is analyzed experimentally in a 65nm bulk CMOS test chip.by Benton H. Calhoun.Ph.D

    Seal whiskers vibrate over broad frequencies during hydrodynamic tracking

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    © The Author(s), 2017. This article is distributed under the terms of the Creative Commons Attribution License. The definitive version was published in Scientific Reports 7 (2017): 8350, doi:10.1038/s41598-017-07676-w.Although it is known that seals can use their whiskers (vibrissae) to extract relevant information from complex underwater flow fields, the underlying functioning of the system and the signals received by the sensors are poorly understood. Here we show that the vibrations of seal whiskers may provide information about hydrodynamic events and enable the sophisticated wake-tracking abilities of these animals. We developed a miniature accelerometer tag to study seal whisker movement in situ. We tested the ability of the tag to measure vibration in excised whiskers in a flume in response to laminar flow and disturbed flow. We then trained a seal to wear the tag and follow an underwater hydrodynamic trail to measure the whisker signals available to the seal. The results showed that whiskers vibrated at frequencies of 100–300 Hz, with a dynamic response. These measurements are the first to capture the incoming signals received by the vibrissae of a live seal and show that there are prominent signals at frequencies where the seal tactogram shows good sensitivity. Tapping into the mechanoreceptive interface between the animal and the environment may help to decipher the functional basis of this extraordinary hydrodynamic detection ability.Funding was provided by the NSF GRFP and NISE section 219 to C. Murphy and by the Office of Naval Research (N000141910468) to B. Calhoun

    Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform

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    We present FASoC, the world’s first autonomous mixed-signal SoC framework driven entirely by user constraints, along with a suite of automated generators for analog blocks. The process agnostic framework takes high-level user intent as inputs to generate optimized and fully verified analog blocks using a cell-based design methodology. Our approach is highly scalable and silicon-proven by an SoC prototype which includes 2 PLLs, 3 LDOs, 1 SRAM, and 2 temperature sensors fully integrated with a processor in a 65nm CMOS process. The physical design of all blocks, including analog, is achieved using optimized synthesis and APR flows in commercially available tools. The framework is portable across different processes and requires no human in the loop, dramatically accelerating design time.This material is based on research sponsored by Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) under agreement number FA8650 18 2 7844. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/165331/1/Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform.pdfDescription of Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform.pdf : Main articleSEL

    Brain Structural Networks Associated with Intelligence and Visuomotor Ability

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    Increasing evidence indicates that multiple structures in the brain are associated with intelligence and cognitive function at the network level. The association between the grey matter (GM) structural network and intelligence and cognition is not well understood. We applied a multivariate approach to identify the pattern of GM and link the structural network to intelligence and cognitive functions. Structural magnetic resonance imaging was acquired from 92 healthy individuals. Source-based morphometry analysis was applied to the imaging data to extract GM structural covariance. We assessed the intelligence, verbal fluency, processing speed, and executive functioning of the participants and further investigated the correlations of the GM structural networks with intelligence and cognitive functions. Six GM structural networks were identified. The cerebello-parietal component and the frontal component were significantly associated with intelligence. The parietal and frontal regions were each distinctively associated with intelligence by maintaining structural networks with the cerebellum and the temporal region, respectively. The cerebellar component was associated with visuomotor ability. Our results support the parieto-frontal integration theory of intelligence by demonstrating how each core region for intelligence works in concert with other regions. In addition, we revealed how the cerebellum is associated with intelligence and cognitive functions

    Effects of Anacetrapib in Patients with Atherosclerotic Vascular Disease

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    BACKGROUND: Patients with atherosclerotic vascular disease remain at high risk for cardiovascular events despite effective statin-based treatment of low-density lipoprotein (LDL) cholesterol levels. The inhibition of cholesteryl ester transfer protein (CETP) by anacetrapib reduces LDL cholesterol levels and increases high-density lipoprotein (HDL) cholesterol levels. However, trials of other CETP inhibitors have shown neutral or adverse effects on cardiovascular outcomes. METHODS: We conducted a randomized, double-blind, placebo-controlled trial involving 30,449 adults with atherosclerotic vascular disease who were receiving intensive atorvastatin therapy and who had a mean LDL cholesterol level of 61 mg per deciliter (1.58 mmol per liter), a mean non-HDL cholesterol level of 92 mg per deciliter (2.38 mmol per liter), and a mean HDL cholesterol level of 40 mg per deciliter (1.03 mmol per liter). The patients were assigned to receive either 100 mg of anacetrapib once daily (15,225 patients) or matching placebo (15,224 patients). The primary outcome was the first major coronary event, a composite of coronary death, myocardial infarction, or coronary revascularization. RESULTS: During the median follow-up period of 4.1 years, the primary outcome occurred in significantly fewer patients in the anacetrapib group than in the placebo group (1640 of 15,225 patients [10.8%] vs. 1803 of 15,224 patients [11.8%]; rate ratio, 0.91; 95% confidence interval, 0.85 to 0.97; P=0.004). The relative difference in risk was similar across multiple prespecified subgroups. At the trial midpoint, the mean level of HDL cholesterol was higher by 43 mg per deciliter (1.12 mmol per liter) in the anacetrapib group than in the placebo group (a relative difference of 104%), and the mean level of non-HDL cholesterol was lower by 17 mg per deciliter (0.44 mmol per liter), a relative difference of -18%. There were no significant between-group differences in the risk of death, cancer, or other serious adverse events. CONCLUSIONS: Among patients with atherosclerotic vascular disease who were receiving intensive statin therapy, the use of anacetrapib resulted in a lower incidence of major coronary events than the use of placebo. (Funded by Merck and others; Current Controlled Trials number, ISRCTN48678192 ; ClinicalTrials.gov number, NCT01252953 ; and EudraCT number, 2010-023467-18 .)

    Circuit techniques for subthreshold leakage reduction in a deep sub-micron process

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    Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 115-118).by Benton Highsmith Calhoun.S.M
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