Electromigration Behavior of 3D-IC TSV

International audienc

Electromigration Behavior of 3D-IC TSV

International audienc

Resistance Increase Due to Electromigration Induced Depletion Under TSV

ISBN 978-1-4244-9111-7International audience3D-IC integration using Through Silicon Via (TSV) is becoming an alternative to overcome obstacles of CMOS scaling. As TSV processes reach maturity, reliability investigation becomes critical. To the best of our knowledge, we propose for the first time an analytical model of resistance increase due to electromigration induced voiding in a line ended by a TSV

Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric

International audienceIn this paper, reliability of Through Silicon via (TSV) interconnects is analyzed for two technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2 μm diameter and 15 μm of depth. Thermal cycling and electromigration stresses are performed on dedicated devices. Thermal cycling is revealed to induce only defects on non-mature processes. Electromigration induces voids in adjacent metal level, right at TSV interface. Moreover, the expected lifetime benefit by increasing line thickness does not occur due to increasing dispersion of voiding mechanism. Second part covers reliability of Cu TSV-middle technology, of 10 μm diameter and 80 μm depth, with thermal cycling, BEoL dielectric breakdown, and electromigration study. Thermal cycling is assessed on two designs: isolated and dense TSV patterns. Dielectric breakdown tests underline an impact of TSV on the reliability of metal level dielectrics right above TSV. Electromigration reveal similar degradation mechanism and kinetic as on TSV-last approach

RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking

International audienc

"RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking"

International audienc

Caractérisation en hyperfréquences et modélisation de Vias Traversant le Silicium pour l'intégration de puces tridimensionnelles

National audienc