Automating the IEEE std. 1500 compliance verification for embedded cores

The IEEE 1500 standard for embedded core testing proposes a very effective solution for testing modern system-on-chip (SoC). It proposes a flexible hardware test wrapper architecture, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Already several IP providers have announced compliance in both existing and future design blocks. In this paper we address the challenge of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE std. 1500. This is a mandatory step to fully trust the wrapper functionalities in applying the test sequences to the core. The proposed solution aims at implementing a verification framework allowing core providers and/or integrators to automatically verify the compliancy of their products (sold or purchased) to the standar

Are IEEE 1500 compliant cores really compliant to the standard?

Functional verification of complex SoC designs is a challenging task, which fortunately is increasingly supported by automation. This article proposes a verification component for IEEE Std 1500, to be plugged into a commercial verification tool suit

Memory Fault Simulator for Static-Linked Faults

Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design and validation a very complex task. This paper presents a memory fault simulator architecture targeting the full set of linked fault

LOWER PLIOCENE BARNACLE FACIES OF WESTERN LIGURIA (NW ITALY): A PEEK INTO A WARM PAST AND A GLIMPSE OF OUR INCOMING FUTURE

The lower Pliocene deposits of Pairola (Liguria, Italy) display the otherwise rare occurrence of rock-forming amounts of barnacles (mostly belonging to the extinct Euromediterranean species Concavus concavus). Three main facies are recognised in the investigated succession: a barnacle-dominated facies, which formed along a shallow (<15 m deep) nearshore environment, a foraminifera-dominated facies from relatively deeper waters (40-100 m), and an intermediate facies forming at the boundary of the other two. These facies and their relationships suggest deposition in a flooded valley – a kind of setting that was common in the Mediterranean after the Messinian Salinity Crisis. Differing from other rias, the Pairola basin was exposed to strong waves, resulting in conditions favourable to barnacles. Sedimentological and stratigraphic observations indicate that the Pairola succession formed within a timespan covering both cold and warm phases. This is relevant because the sub-tropical foraminifer Amphistegina is ubiquitous throughout the succession. Amphistegina occurs in the Pliocene and lower Pleistocene (Gelasian) of Northern Italy, but not in the remainder of the Pleistocene, not even its warm portions. This genus is currently recolonizing the Mediterranean and is projected to reach the northern coast of the basin soon, foretelling that Anthropocene temperatures are going to overcome those of the late Pleistocene warm periods and reach those of the Pliocene

March AB, March AB1: new March tests for unlinked dynamic memory faults

Among the different types of algorithms proposed to test static random access memories (SRAMs), March tests have proven to be faster, simpler and regularly structured. New memory production technologies introduce new classes of faults usually referred to as dynamic memory faults. A few March tests for dynamic fault, with different fault coverage, have been published. In this paper, we propose new March tests targeting unlinked dynamic faults with lower complexity than published ones. Comparison results show that the proposed March tests provide the same fault coverage of the known ones, but they reduce the test complexity, and therefore the test tim

A 22n March Test for Realistic Static Linked Faults in SRAMs

Linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design a very complex task. Although several March tests have been developed for the wide memory faults spread, a few of them are able to detect linked faults. In the present paper March AB, a March test targeting the set of realistic memory linked fault is presented. Comparison results show that the proposed March test provides the same fault coverage of already published algorithms but, it reduces the test complexity and therefore the test time. Moreover, a complete taxonomy of linked faults will be presente

Test and Diagnosis of Integrated Circuits

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users, the manufacturing process is becoming finer and denser, making chips more prone to defects.The work presented in the HDR manuscript addresses the challenges of test and diagnosis of integrated circuits. It covers:- Power aware test;- Test of Low Power Devices;- Fault Diagnosis of digital circuits

A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs

Among the different types of algorithms proposed to test static random access memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. A large number of march tests with different fault coverage have been published. Usually different march tests detect only a specific set of memory faults. The always growing memory production technology introduces new classes of fault, making a key hurdle the generation of new march tests. The aim of this paper is to target the whole set of realistic fault model and to provide a unique march test able to reduce the test complexity of 15.4% than state-of-the-art march algorith

Automatic March tests generation for static and dynamic faults in SRAMs

New memory production modern technologies introduce new classes of faults usually referred to as dynamic memory faults. Although some hand-made March tests to deal with these new faults have been published, the problem of automatically generate March tests for dynamic faults has still to be addressed, in this paper we propose a new approach to automatically generate March tests with minimal length for both static and dynamic faults. The proposed approach resorts to a formal model to represent faulty behaviors in a memory and to simplify the generation of the corresponding tests

March Test Generation Revealed

Memory testing commonly faces two issues: the characterization of detailed and realistic fault models and the definition of time-efficient test algorithms. Among the different types of algorithms proposed for testing static random access memories, march tests have proven to be faster, simpler, and regularly structured. The majority of the published march tests have been manually generated. Unfortunately, the continuous evolution of the memory technology introduces new classes of faults such as dynamic and linked faults and makes the task of handwriting test algorithms harder and not always leading to optimal results. Although some researchers published handmade march tests able to deal with new fault models, the problem of a comprehensive methodology to automatically generate march tests addressing both classic and new fault models is still an open issue. This paper proposes a new polynomial algorithm to automatically generate march tests. The formal model adopted to represent memory faults allows the definition of a general methodology to deal with static, dynamic, and linked faults. Experimental results show that the new automatically generated march tests reduce the test complexity and, therefore, the test time, compared to the well-known state of the art in memory testin