Among the different types of algorithms proposed to test static random access memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. A large number of march tests with different fault coverage have been published. Usually different march tests detect only a specific set of memory faults. The always growing memory production technology introduces new classes of fault, making a key hurdle the generation of new march tests. The aim of this paper is to target the whole set of realistic fault model and to provide a unique march test able to reduce the test complexity of 15.4% than state-of-the-art march algorith

Benso, Alfredo

Bosio, Alberto

Di Carlo, Stefano

Di Natale, Giorgio

Prinetto, Paolo Ernesto

English

BENSO, Alfredo

BOSIO, ALBERTO

DI CARLO, STEFANO

DI NATALE, Giorgio

PRINETTO, Paolo Ernesto

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

05 August 2020POLITECNICO DI TORINORepository ISTITUZIONALEA Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs / Benso A.; Bosio A.; Di CarloS.; Di Natale G.; Prinetto P.. - STAMPA. - (2006), pp. 155-156. ((Intervento presentato al convegno IEEE 9th Workshopon Design and Diagnostics of Electronic Circuits and Systems (DDECS) tenutosi a Prague, CZ nel 18-21 Apr. 2006.OriginalA Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMsPublisher:PublishedDOI:10.1109/DDECS.2006.1649602Terms of use:openAccessPublisher copyright(Article begins on next page)This article is made available under terms and conditions as specified in the  corresponding bibliographic description inthe repositoryAvailability:This version is available at: 11583/1499963 since:IEEE Computer SocietyA Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs   A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto Politecnico di Torino Dipartimento di Automatica e Informatica  Torino, Italy E-mail {benso, bosio, dicarlo, dinatale, prinetto}@polito.it http://www.testgroup.polito.it  Abstract-Among the different types of algorithms proposed to test Static Random Access Memories (SRAMs), March Tests have proven to be faster, simpler and regularly structured. A large number of March Tests with different fault coverage have been published. Usually different march tests detect only a specific set of memory faults. The always growing memory production technology introduces new classes of fault, making a key hurdle the generation of new march tests. The aim of this paper is to target the whole set of realistic fault model and to provide a unique march test able to reduce the test complexity of 15.4% than state-of-the-art march algorithm.  1. INTRODUCTION  Memories are one of the most important components in digital systems, and semiconductor memories are nowadays one of the fastest growing technologies. System-On-a-Chip (SOC) technologies allow to embed in a single chip all the components and functions that historically were placed on a hardware board. Within SOCs, embedded memories are the densest components, accounting for up to 90% of chips area [1]. It is thus common finding, on a single chip, tens of memories of different types, sizes, access protocols and timing. Moreover they can recursively be embedded in embedded cores.  In the latest decade published researches mainly focused on the definition of new fault models [2] [3] [4]. The high number of fault models can be reduced considering so called Realistic Faults only. Those faults have been proved to be realistic by performing fault injection and circuit simulation experiments [4][8][9].  The realistic fault models can be clustered in three main fault sets: (i) static un-linked (ii) dynamic un-linked and (iii) static linked faults. [8].  Up to now, researchers mainly focused on the minimization of existing memory tests for a single target fault set [5] [6] [7]. In case of complex fault lists, the typical test strategy is to apply several march tests customized for the different fault sets. As an example to detect both static un-linked and static linked faults a typical approach is to apply a march test for static un-linked faults followed by a test algorithm for static linked fault. The main lack of this solution is the time effort. It is the sum of the complexity of the two march tests. Moreover, since some fault models are usually detected by both the algorithms the resulting strategy is redundant. The aim of this work is to propose a unique non redundant march test able to detect the whole set of realistic fault models (static un-linked, dynamic un-linked and, static linked faults). The proposed solution reduces the test effort of about 15.4% w.r.t state of the art algorithms by applying just a single march test having a complexity of 22n. The paper is structured as follows: Section 2 introduces the fault taxonomy; Section 3 and Section 4 introduce the proposed solution. Section 5 summarizes the main contributions and outlines future research activities.  2. FAULT MODEL TAXONOMY  For test purposes, faults in memories are usually modeled as Functional Faults. A Functional Fault Model (FFM) is a deviation of the memory behavior from the expected one under a set of performed operations.  Each FFM can be described by a set of Fault Primitives (FPs) [9].  In this paper we focus on the following sets of realistic fault models:  ‚ Static un-linked faults (TABLE 1 and TABLE 4) ‚ Dynamic un-linked faults : (TABLE 2 and TABLE 5) ‚ Static linked faults: described in TABLE 3 and  TABLE 6. They are composed by a combination of static un-linked faults as described in definition 1.  Definition 1 : two FPs, FP1 = <S1/F1/R1> and FP2 = <S2/F2/R2>, are said to be  Linked, and denoted by  1-4244-0185-2/06/$20.00 c©2006 IEEE“FP1 › FP2”, if both of the following conditions are satisfied: ‚ FP2 masks FP1, i.e., F2 = not (F1);  ‚ Read operations of FP1 and FP2 don’t detect a fault. ‚ The Sensitizing operation (S2) of FP2 is applied after S1, on either the a-cell or v-cell of FP1.  TABLE 1 Single Cell Static Un-linked Faults FFM FPs SF <x / y> WDF <ywy / x / -> TF <xwy / x / -> RDF <xrx / y / y> DRDF <yry / x / y> IRF <yry / x / y>  TABLE 2 Single Cell Dynamic Un-linked Faults FFM FPs dRDF <zwxrx / y / y> dDRDF <zwxrx / y / x> dIRF <zwxrx / x / y>  TABLE 3 Single Cell Static Linked Faults Linked Fault FPs FP1 FP1›WDF FP1 › <xwx / y / -> TF, WDF, DRDF FP1› RDF FP1 › <xrx / y / y> TF, WDF, DRDF  TABLE 4 Two Cell Static Un-linked Faults, z, k, x, y Œ {0,1}, x = not(y), z = not(k)  FFM FPs CFst <z ; x / y /-> CFds <zrz ; x / y / ->, <zwz ; x / y / ->, <zwk ; x / y / ->  CFtr <z ; xwy / x / -> CFwd <z ; xwx / y / -> CFrd <z ; xrx / y / y> CFdr <z ; xrx / y / x> CFir <z ; xrx / x / y>  TABLE 5 Two Cell Dynamic Un-linked Faults, , z, k, x, y Œ {0,1}, x = not(y), z = not(k) FFM FPs dCFds <zwkrk ; x / y / -> dCFrd <z ; kwxrx / y / y> dCFdrd <z ; kwxrx / y / x> dCFir <z ; kwxrx / x / y>  TABLE 6 Two Cell Static Linked Faults Type Linked Fault FP1 FP1 ›CFds CFds, CFtr, CFwd, CFdr FP1›CFwd CFds, CFtr, CFwd, CFdr LF2aa FP1›CFrd CFds, CFtr, CFwd, CFdr FP1›WDF CFds, CFtr, CFwd, CFdr LF2av FP1›RDF CFds, CFtr, CFwd, CFdr FP1 ›CFds WDF, TF, DRDF FP1›CFwd WDF, TF, DRDF LF2va FP1›CFrd WDF, TF, DRDF  3. FAULT DETECTION  Single cell faults can be detected by two Fault Coverage Conditions:  ‚ FCC1 = >(ry,wx,rx,wx,rx) >(rx…) ‚ FCC2 = >(rx,wy,ry,wy,ry) >(ry…)  Two cell faults can be detected by the following FCC: ‚ FCC3 : ¹(rx,wy,ry,wy,ry)¹(ry,wx,rx,wx,rx) ³(rx,wy,ry,wy,ry)³(ry,wx,rx,wx,rx) >(rx,...)  4. MARCH SOLUTION  March AB [10] shown in Fig. 1, contains all the FCCs required to cover the full set of realistic memory faults. {>(w0) ¹(r0,w1,r1,w1,r1)  ¹(r1,w0,r0,w0,r0) ³(r0,w1,r1,w1,r1)      M0             M1               M2    M3 ³(r1,w0,r0,w0,r0) >(r0)}                      M4    M5 Fig. 1 :  March AB. 5. CONCLUSIONS  This paper proposed a new March Test targeting the entire set of realistic memory faults. Our test provides the same coverage of the state-of-the-art test algorithms but reducing test complexity of 15.4% and therefore the test time. It makes possible resort to a single march test able to detect the bigger set of realistic memory fault, therefore March AB becomes a natural candidate for memory BIST architectures, building our test solution very attractive for the industry.   REFERENCES [1] International Technology Roadmap for Semiconductors,     “International technology roadmap for semiconductors 2004 Update”, http://public.itrs.net/Home.htm, 2004. [2] R. Dekker, F. Beenker, L. Thijssen, “A Realistic Fault Model and Test Algorithms for Satic Random Acces Memory”, IEEE Transaction on Computer-Aided Design, Volume: 9, Issue: 6, June 1990. [3] R.D. Adams and E.S. Cooley, “Analysis of a Deceptive Destructive Read Memory fault Model and Recommended Testing”, NATW 1996. 5th IEEE North Atlantic Test Workshop, 1996 . [4] Z. Al-Ars, Ad J. van de Goor, “Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs”, DATE 2001, IEEE Design Automation and Test in Europe, 2001,  pp. 496-503. [5] A. J. van de Goor, G.N. Gayadadjiev, V.N. Yarmolik, V.G. Mikitjuk, “March LA: A Test for Linked Memory Faults”, ED&TC 1997, Proc. European Design and Test Conference, 1997, pp. 167. [6] A. J. van de Goor, G.N. Gayadadjiev, V.N. Yarmolik, V.G. Mikitjuk, “March LR: A Test for Realistic Linked Faults”,  VTS 1996, 16th IEEE VLSI Test Symposium, 1996, pp. 272-280. [7] S.M. Al-Harbi, S.K. Gupta, “Generating Complete and Optimal March Tests for Linked Faults in Memories”, VTS 2003, 21th IEEEVLSI Test Symposium, 2003, pp.  254 -261. [8] S. Hamdioui, Z. Al-Ars, A. J. van de Goor, M. Rodgers, “Linked Faults in Random Access Memories Concept Fault Models Test Algorithms and Industrial Results”, IEEE Transaction on Computer-Aided Design, Volume: 23, Issue: 5, May 2004, pp. 737-757. [9] A. J. van de Goor, Z. Al-Ars, “Functional Memory Faults: A Formal Notation and a Taxonomy”, VTS 2000, 18th IEEE VLSI Test Symposium, 2000, pp. 281-289. [10] A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto, “March AB, March AB1: New March Tests for Unlinked Dynamic Memory Faults”, ITC 2005, IEEE International Test Conference, 2005. 

A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs

PORTO Publications Open Repository TOrino

A Unique March Test Algorithm for the Wide 
Spread of 
Realistic Memory Faults in SRAMs  
 
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto 
Politecnico di Torino 
Dipartimento di Automatica e Informatica  
Torino, Italy 
E-mail {benso, bosio, dicarlo, dinatale, prinetto}@polito.it 
http://www.testgroup.polito.it 
 
Abstract-Among the different types of algorithms 
proposed to test Static Random Access Memories (SRAMs), 
March Tests have proven to be faster, simpler and regularly 
structured. A large number of March Tests with different 
fault coverage have been published. Usually different march 
tests detect only a specific set of memory faults. 
The always growing memory production technology 
introduces new classes of fault, making a key hurdle the 
generation of new march tests. The aim of this paper is to 
target the whole set of realistic fault model and to provide a 
unique march test able to reduce the test complexity of 
15.4% than state-of-the-art march algorithm. 
 
1. INTRODUCTION 
 
Memories are one of the most important components 
in digital systems, and semiconductor memories are 
nowadays one of the fastest growing technologies. 
System-On-a-Chip (SOC) technologies allow to embed in 
a single chip all the components and functions that 
historically were placed on a hardware board. Within 
SOCs, embedded memories are the densest components, 
accounting for up to 90% of chips area [1]. It is thus 
common finding, on a single chip, tens of memories of 
different types, sizes, access protocols and timing. 
Moreover they can recursively be embedded in embedded 
cores.  
In the latest decade published researches mainly 
focused on the definition of new fault models [2] [3] [4]. 
The high number of fault models can be reduced 
considering so called Realistic Faults only. Those faults 
have been proved to be realistic by performing fault 
injection and circuit simulation experiments [4][8][9]. 
 The realistic fault models can be clustered in three 
main fault sets: (i) static un-linked (ii) dynamic un-linked 
and (iii) static linked faults. [8].  
Up to now, researchers mainly focused on the 
minimization of existing memory tests for a single target 
fault set [5] [6] [7]. In case of complex fault lists, the 
typical test strategy is to apply several march tests 
customized for the different fault sets. As an example to 
detect both static un-linked and static linked faults a 
typical approach is to apply a march test for static un-
linked faults followed by a test algorithm for static linked 
fault. The main lack of this solution is the time effort. It is 
the sum of the complexity of the two march tests. 
Moreover, since some fault models are usually detected 
by both the algorithms the resulting strategy is redundant. 
The aim of this work is to propose a unique non 
redundant march test able to detect the whole set of 
realistic fault models (static un-linked, dynamic un-linked 
and, static linked faults). The proposed solution reduces 
the test effort of about 15.4% w.r.t state of the art 
algorithms by applying just a single march test having a 
complexity of 22n. 
The paper is structured as follows: Section 2 
introduces the fault taxonomy; Section 3 and Section 4 
introduce the proposed solution. Section 5 summarizes 
the main contributions and outlines future research 
activities. 
 
2. FAULT MODEL TAXONOMY 
 
For test purposes, faults in memories are usually 
modeled as Functional Faults. A Functional Fault Model 
(FFM) is a deviation of the memory behavior from the 
expected one under a set of performed operations.  
Each FFM can be described by a set of Fault 
Primitives (FPs) [9].  
In this paper we focus on the following sets of realistic 
fault models:  
‚ Static un-linked faults (TABLE 1 and TABLE 4) 
‚ Dynamic un-linked faults : (TABLE 2 and TABLE 5) 
‚ Static linked faults: described in TABLE 3 and  
TABLE 6. They are composed by a combination of 
static un-linked faults as described in definition 1. 
 
Definition 1 : two FPs, FP1 = <S1/F1/R1> and FP2 = 
<S2/F2/R2>, are said to be  Linked, and denoted by  
1-4244-0185-2/06/$20.00 c©2006 IEEE
“FP1 › FP2”, if both of the following conditions are 
satisfied: 
‚ FP2 masks FP1, i.e., F2 = not (F1);  
‚ Read operations of FP1 and FP2 don’t detect a 
fault. 
‚ The Sensitizing operation (S2) of FP2 is applied 
after S1, on either the a-cell or v-cell of FP1. 
 
TABLE 1 Single Cell Static Un-linked Faults 
FFM FPs 
SF <x / y> 
WDF <ywy / x / -> 
TF <xwy / x / -> 
RDF <xrx / y / y> 
DRDF <yry / x / y> 
IRF <yry / x / y> 
 
TABLE 2 Single Cell Dynamic Un-linked Faults 
FFM FPs 
dRDF <zwxrx / y / y> 
dDRDF <zwxrx / y / x> 
dIRF <zwxrx / x / y> 
 
TABLE 3 Single Cell Static Linked Faults 
Linked Fault FPs FP1 
FP1›WDF FP1 › <xwx / y / -> TF, WDF, DRDF 
FP1› RDF FP1 › <xrx / y / y> TF, WDF, DRDF 
 
TABLE 4 Two Cell Static Un-linked Faults, z, k, x, y Œ {0,1}, x = not(y), z = not(k)  
FFM FPs 
CFst <z ; x / y /-> 
CFds <zrz ; x / y / ->, <zwz ; x / y / ->, <zwk ; x / y / ->  
CFtr <z ; xwy / x / -> 
CFwd <z ; xwx / y / -> 
CFrd <z ; xrx / y / y> 
CFdr <z ; xrx / y / x> 
CFir <z ; xrx / x / y> 
 
TABLE 5 Two Cell Dynamic Un-linked Faults, , z, k, x, y Œ {0,1}, x = not(y), z = not(k) 
FFM FPs 
dCFds <zwkrk ; x / y / -> 
dCFrd <z ; kwxrx / y / y> 
dCFdrd <z ; kwxrx / y / x> 
dCFir <z ; kwxrx / x / y> 
 
TABLE 6 Two Cell Static Linked Faults 
Type Linked Fault FP1 
FP1 ›CFds CFds, CFtr, CFwd, CFdr 
FP1›CFwd CFds, CFtr, CFwd, CFdr LF2aa 
FP1›CFrd CFds, CFtr, CFwd, CFdr 
FP1›WDF CFds, CFtr, CFwd, CFdr 
LF2av 
FP1›RDF CFds, CFtr, CFwd, CFdr 
FP1 ›CFds WDF, TF, DRDF 
FP1›CFwd WDF, TF, DRDF LF2va 
FP1›CFrd WDF, TF, DRDF 
 
3. FAULT DETECTION 
 
Single cell faults can be detected by two Fault 
Coverage Conditions:  
‚ FCC1 = >(ry,wx,rx,wx,rx) >(rx…) 
‚ FCC2 = >(rx,wy,ry,wy,ry) >(ry…) 
 
Two cell faults can be detected by the following FCC: 
‚ FCC3 : ¹(rx,wy,ry,wy,ry)¹(ry,wx,rx,wx,rx) 
³(rx,wy,ry,wy,ry)³(ry,wx,rx,wx,rx) >(rx,...) 
 
4. MARCH SOLUTION 
 
March AB [10] shown in Fig. 1, contains all the FCCs 
required to cover the full set of realistic memory faults. 
{>(w0) ¹(r0,w1,r1,w1,r1)  ¹(r1,w0,r0,w0,r0) ³(r0,w1,r1,w1,r1) 
     M0             M1               M2    M3 
³(r1,w0,r0,w0,r0) >(r0)} 
                     M4    M5 
Fig. 1 :  March AB. 
5. CONCLUSIONS 
 
This paper proposed a new March Test targeting the 
entire set of realistic memory faults. Our test provides the 
same coverage of the state-of-the-art test algorithms but 
reducing test complexity of 15.4% and therefore the test 
time. It makes possible resort to a single march test able 
to detect the bigger set of realistic memory fault, therefore 
March AB becomes a natural candidate for memory BIST 
architectures, building our test solution very attractive for 
the industry.  
 
REFERENCES 
[1] International Technology Roadmap for Semiconductors,     
“International technology roadmap for semiconductors 2004 Update”, 
http://public.itrs.net/Home.htm, 2004. 
[2] R. Dekker, F. Beenker, L. Thijssen, “A Realistic Fault Model and 
Test Algorithms for Satic Random Acces Memory”, IEEE Transaction 
on Computer-Aided Design, Volume: 9, Issue: 6, June 1990. 
[3] R.D. Adams and E.S. Cooley, “Analysis of a Deceptive Destructive 
Read Memory fault Model and Recommended Testing”, NATW 1996. 
5th IEEE North Atlantic Test Workshop, 1996 . 
[4] Z. Al-Ars, Ad J. van de Goor, “Static and Dynamic Behavior of 
Memory Cell Array Opens and Shorts in Embedded DRAMs”, DATE 
2001, IEEE Design Automation and Test in Europe, 2001,  pp. 496-503. 
[5] A. J. van de Goor, G.N. Gayadadjiev, V.N. Yarmolik, V.G. Mikitjuk, 
“March LA: A Test for Linked Memory Faults”, ED&TC 1997, Proc. 
European Design and Test Conference, 1997, pp. 167. 
[6] A. J. van de Goor, G.N. Gayadadjiev, V.N. Yarmolik, V.G. Mikitjuk, 
“March LR: A Test for Realistic Linked Faults”,  VTS 1996, 16th IEEE 
VLSI Test Symposium, 1996, pp. 272-280. 
[7] S.M. Al-Harbi, S.K. Gupta, “Generating Complete and Optimal 
March Tests for Linked Faults in Memories”, VTS 2003, 21th 
IEEEVLSI Test Symposium, 2003, pp.  254 -261. 
[8] S. Hamdioui, Z. Al-Ars, A. J. van de Goor, M. Rodgers, “Linked 
Faults in Random Access Memories Concept Fault Models Test 
Algorithms and Industrial Results”, IEEE Transaction on Computer-
Aided Design, Volume: 23, Issue: 5, May 2004, pp. 737-757. 
[9] A. J. van de Goor, Z. Al-Ars, “Functional Memory Faults: A Formal 
Notation and a Taxonomy”, VTS 2000, 18th IEEE VLSI Test 
Symposium, 2000, pp. 281-289. 
[10] A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto, “March 
AB, March AB1: New March Tests for Unlinked Dynamic Memory 
Faults”, ITC 2005, IEEE International Test Conference, 2005. 


A Realistic Fault Model and Test Algorithms for Satic Random Acces Memory”,

Analysis of a Deceptive Destructive Read Memory fault Model and Recommended Testing”,

Functional Memory Faults: A Formal Notation and a Taxonomy”,

Generating Complete and Optimal March Tests for Linked Faults

LA: A Test for Linked Memory Faults”, ED&TC

Linked Faults in Random Access Memories Concept Fault Models Test Algorithms and Industrial Results”,

LR: A Test for Realistic Linked Faults”,

Roadmap for Semiconductors, “International technology roadmap for semiconductors

Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs”,

Tests for Unlinked Dynamic Memory Faults”,

https://iris.polito.it/retrieve/handle/11583/1499963/47090/2006-DDECS-MarchTest.pdf

A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs

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