Risk perception influences athletic pacing strategy.

PURPOSE: The objective of this study is to examine risk taking and risk perception associations with perceived exertion, pacing, and performance in athletes. METHODS: Two experiments were conducted in which risk perception was assessed using the domain-specific risk taking (DOSPERT) scale in 20 novice cyclists (experiment 1) and 32 experienced ultramarathon runners (experiment 2). In experiment 1, participants predicted their pace and then performed a 5-km maximum effort cycling time trial on a calibrated Kingcycle mounted bicycle. Split times and perceived exertion were recorded every kilometer. In experiment 2, each participant predicted their split times before running a 100-km ultramarathon. Split times and perceived exertion were recorded at seven checkpoints. In both experiments, higher and lower risk perception groups were created using median split of DOSPERT scores. RESULTS: In experiment 1, pace during the first kilometer was faster among lower risk perceivers compared with higher risk perceivers (t(18) = 2.0, P = 0.03) and faster among higher risk takers compared with lower risk takers (t(18) = 2.2, P = 0.02). Actual pace was slower than predicted pace during the first kilometer in both the higher risk perceivers (t(9) = -4.2, P = 0.001) and lower risk perceivers (t(9) = -1.8, P = 0.049). In experiment 2, pace during the first 36 km was faster among lower risk perceivers compared with higher risk perceivers (t(16) = 2.0, P = 0.03). Irrespective of risk perception group, actual pace was slower than predicted pace during the first 18 km (t(16) = 8.9, P < 0.001) and from 18 to 36 km (t(16) = 4.0, P < 0.001). In both experiments, there was no difference in performance between higher and lower risk perception groups. CONCLUSIONS: Initial pace is associated with an individual's perception of risk, with low perceptions of risk being associated with a faster starting pace. Large differences between predicted and actual pace suggest that the performance template lacks accuracy, perhaps indicating greater reliance on momentary pacing decisions rather than preplanned strategy.This is the author accepted manuscript. The final version is available from Wolters Kluwer via http://dx.doi.org/10.1249/MSS.000000000000050

Timing errors in sta-based gate-level simulation

In this paper, we demonstrate that conventional STA-based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local slew errors at cutpoints, and secondly because slew propagation may not be upper-bounded across multiple cut points in the same cycle. The use of an ASTA engine, which does not cut cycles, and properly bounds slews across cycles is a possible solution, which can indeed serve as an upper bound over SPICE, transistor level similations. We contrast STA and ASTA-based SDF-Annotated gate-level simulation results, with transistor level SPICE results, and demonstrate the impact of timing errors. © 2020 IEEE

Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits

In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local slew errors at cutpoints, and secondly because slew propagation may not be upper bounded across multiple cut points in the same cycle. The use of an Asynchronous STA (ASTA) engine, which does not cut cycles, and properly bounds slews across cycles is a possible solution, which can indeed serve as an upper bound over SPICE transistor level similations. We contrast STA and ASTA-based gate-level simulations with transistor level SPICE simulations to demonstrate the impact of timing errors for 12 asynchronous control circuits, implemented by the Petrify tool, in a 0.25µm technology library. We show that STA-based simulation results are incorrectly more optimistic than ASTA, and it is possible for the simulation period to even be faster than SPICE, which is a major timing error. © 2021 IEE

Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows

Process variation has proven to be one of the higher impacting factors in modern Application-Specific Integrated Circuit (ASIC) flows Quality of Results (QoR). On the one hand, the excessive MOSFET shrinking, in combination with the less potent metallization layers shrinking ability at cutting edge technology nodes, has rendered process variation effects more and more pronounced. On the other hand, the ever-increasing market competition between hi-tech semiconductor companies has promoted the adoption of immature, emerging technology nodes, which are not adequately calibrated for high yield in mass production. To cope with these issues, the industry has adopted a test-calibrate-produce strategy, meaning that design-specific golden silicon data are obtained by relatively inexpensive test chip fabrication runs and then are used to calibrate the ASIC flow for highest possible yield on expensive mass production, accordingly. These golden data are typically used at the ASIC flow Back-End, i. e. Place & Route, Clock Tree Synthesis, In-Place Optimization, Sign-Off. In this work, we present a deterministic and a Monte-Carlo based methodology, capable of providing an insight of inter-wafer and intra-die process variation impact, at the post-synthesis gate level, to provide a better initial solution to the ASIC Back-End. Both methodologies were tested using four open-source designs for 4 different technology libraries at 250, 130, 40, and 7 nm, and yield 9.74% improvement in total cell area and 22.14% improvement in leakage power, on average, over netlists synthesized at worst case, while meeting worst-case timing for all libraries. Also, our Monte-Carlo methodology provides a predictive view on the random variation impact on netlists synthesized at typical corner. © 2022 IEEE