Inductive power transfer for on-body sensors defining a design space for safe, wirelessly powered on-body health sensors

Pervasive Health: 9th International Conference on Pervasive Computing Technologies for Healthcare, 20-23 May 2015, Istanbul, TurkeyDesigners of on-body health sensing devices face a difficult choice. They must either minimise the power consumption of devices, which in reality means reducing the sensing capabilities, or build devices that require regular battery changes or recharging. Both options limit the effectiveness of devices. Here we investigate an alternative. This paper presents a method of designing safe, wireless, inductive power transfer into on-body sensor products. This approach can produce sensing devices that can be worn for longer durations without the need for human intervention, whilst also having greater sensing and data capture capabilities. The paper addresses significant challenges in achieving this aim, in particular: device safety, sufficient power transfer, and human factors regarding device geometry. We show how to develop a device that meets stringent international safety guidelines for electromagnetic energy on the body and describe a design space that allows designers to make trade-offs that balance power transfer with other constraints, e.g. size and bulk, that affect the wearability of devices. Finally we describe a rapid experimental method to investigate the optimal placement of on-body devices and the actual versus theoretical power transfer for on-body, inductively powered devices. EPSR

Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance

A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays