GENETIC SCHEDULING OF TASK GRAPHS

A genetic algorithm for scheduling computational task graphs is presented. The problem of assigning tasks to processing elements as a combinatorital optimization is formulated, and a heuristic based on a genetic algorithm is presented. The objective function to be minimized is the 'time on completion\ of all tasks. Results are compared with those published in the literature and with randomly generated task graphs whose optimal schedules are known a priori

GSA: Scheduling and Allocation using Genetic Algorithm

This paper describes a unique approach to schedul- ing and allocation problem in high-level synthesis us- ing genetic algorithm (GA). This approach is di�er- ent from a previous attempt using GA [1] in many respects. Our contributions include: a new chromo- somal representation for scheduling and two subprob- lems of allocation; and two novel crossover operators to generate legal schedules. The approach has been tested on various benchmarks and results are com- pared with those obtained by other approaches such as simulated evolution, tabu search, HAL, SALSA II, STAR, etc

GAP - A GENETIC ALGORITHM APPROACH TO OPTIMIZE 2-BIT DECODER PLAS

PLAs with two bit decoders at the inputs require a smaller area compared with standard two level PLAs. The number of product rows required for such PLas is a function of the assignment of pairs of variables to the decoders. This paper describes a minimization procedure that uses a genetic algorithm approach to reduce the size to the two bit decoder PLAs. Results are compared with those obtained by other approaches such as the Tomczuk and MIller heuristic and the simulated annealing technique (Abd-el-Barr and Choy 1993). For large randomly generated test cases and benchmarks, our results are optimal or very near optimal

Scheduling and allocation in high-level synthesis using stochastic techniques

High-level synthesis is the process of automatically translating abstract behavioral models of digital systems to implementable hardware. Operation scheduling and hardware allocation are the two most important phases in the synthesis of circuits from behavioral specification. Scheduling and allocation can be formulated as an optimization problem. In this work, a unique approach to scheduling and allocation problem using the genetic algorithm (GA) is described. This approach is different from a previous attempt using GA (Wehn et al., IFIP Working Conference on Logic and Architecture Synthesis, Paris, 1990, pp. 47–56) in many respects. The main contributions include: (1) a new chromosomal representation for scheduling and for two subproblems of allocation; and (2) two novel crossover operators to generate legal schedules. In addition the application of tabu search (TS) to scheduling and allocation is also implemented and studied. Two implementations of TS are reported and compared. Both genetic scheduling and allocation (GSA) and tabu scheduling and allocation (TSA) have been tested on various benchmarks and results obtained for data-oriented control-data flow graphs are compared with other implementations in the literature. (A discussion on GSA was presented at the European Design Automation Conference Euro-DAC'94 in Grenoble, France, and TSA at the International Conference on Electronics, Circuits and Systems — ICECS'94 in Cairo, Egypt.) A novel interconnect optimization technique using the GA is also realized

Timing Influenced General-Cell Genetic Floorplanner

In this paper we present a timing-influenced floorplanner for general cell IC design. The floorplanner works in 2 pahses. In the first phase we restirct the modules to be rigid and the floorplan to be slicing. The second phase of floorplanner allows modification to the aspect ratios of indivisual modules to furhter reduce the area of the overall bounding box. The first phase is implemented using a genetic algorithm while in the second phase we adopt a constraint graph based approach. Experimental results are also presented

Scheduling and allocation in high-level synthesis using stochastic techniques

High-level synthesis is the process of automatically translating abstract behavioral models of digital systems to implementable hardware. Operation scheduling and hardware allocation are the two most important phases in the synthesis of circuits from behavioral specification. Scheduling and allocation can be formulated as an optimization problem. In this work, a unique approach to scheduling and allocation problem using the genetic algorithm (GA) is described. This approach is different from a previous attempt using GA (Wehn et al., IFIP Working Conference on Logic and Architecture Synthesis, Paris, 1990, pp. 47–56) in many respects. The main contributions include: (1) a new chromosomal representation for scheduling and for two subproblems of allocation; and (2) two novel crossover operators to generate legal schedules. In addition the application of tabu search (TS) to scheduling and allocation is also implemented and studied. Two implementations of TS are reported and compared. Both genetic scheduling and allocation (GSA) and tabu scheduling and allocation (TSA) have been tested on various benchmarks and results obtained for data-oriented control-data flow graphs are compared with other implementations in the literature. (A discussion on GSA was presented at the European Design Automation Conference Euro-DAC'94 in Grenoble, France, and TSA at the International Conference on Electronics, Circuits and Systems — ICECS'94 in Cairo, Egypt.) A novel interconnect optimization technique using the GA is also realized

Timing Influenced Force Directed Floorplanning

We represent a timing driven floorplanning program for general cell layouts. The approach used combines quality of force directed approach wit that of constraint graph approach. A floorplan solution is produced in two steps. First a timing and connectivity driven topological arrangement is obtained using a force directed approach. In the second step, the topoligical arrangement is trasnformed into a legal floorplan. The objective of the second step is to minimize the overall area of the floorplan. The floorplanner is validated with circuits of sizes varying from 7-125 block