We represent a timing driven floorplanning program for general cell layouts. The approach used combines quality of force directed approach wit that of constraint graph approach. A floorplan solution is produced in two steps. First a timing and connectivity driven topological arrangement is obtained using a force directed approach. In the second step, the topoligical arrangement is trasnformed into a legal floorplan. The objective of the second step is to minimize the overall area of the floorplan. The floorplanner is validated with circuits of sizes varying from 7-125 block
