5 research outputs found
Modeling and simulation of polycrystalline ZnO thin-film transistors
Thin film transistors (TFTs) made of transparent channel semiconductors such
as ZnO are of great technological importance, because their insensitivity to
visible light makes device structures simple. In fact, several demonstrations
are made on ZnO TFT achieving reasonably good field effect mobilities of 1-10
cm2/Vs, but reveal insufficient device performances probably due to the
presence of dense grain boundaries. We have modeled grain boundaries in ZnO
thin film transistors (TFTs) and performed device simulation using a
two-dimensional device simulator for understanding the grain boundary effects
on the device performance. Actual polycrystalline ZnO TFT modeling is commenced
with considering a single grain boundary in the middle of the TFT channel
formulating with a Gaussian defect distribution localized in the grain
boundary. A double Shottky barrier is formed in the grain boundary and its
barrier height are analyzed as functions of defect density and gate bias. The
simulation is extended to the TFTs with many grain boundaries to quantitatively
analyze the potential profiles developed along the channel. One of the big
contrasts of polycrystalline ZnO TFT compared with a polycrystalline Si TFT is
that much smaller nanoscaled grain size induces heavy overlap of double Shottky
barriers. Through the simulation, we can estimate the total trap state density
localized in the grain boundaries for a polycrystalline ZnO by knowing apparent
mobility and grain size in the device.Comment: Submitted to Journal of Applied Physic