The Effect of Education Decentralization on School Leadership in the Vocational Schools: A Comparative Study between the German and the Egyptian Practice

Gershberg (1999) defines education decentralization as the transfer of some of the political, administrative, and/or financial authorities and responsibilities from the central government to the local governments, local units or the schools themselves. In this qualitative study the effect of education decentralization on vocational school leadership is explored. Through conducting structural interviews with 30 school principals in Germany and Egypt, the study was able to reach at three main conclusions. 1- Political decentralization encourages the adoption of participatory leadership by involving the stakeholders in the decision-making process and allowing the schools to set their goals and objectives discretionally. 2- Administrative decentralization encourages the adoption of shared instructional leadership by devolving authorities of teacher selection, evaluation, training and team-building to the schools. And 3- financial decentralization encourages the adoption of entrepreneurial leadership by encouraging the schools to raise funds and deploy the available resources discretionally

Islamismus bei Jugendlichen in empirischen Studien. Ein narratives Review

Der Begriff Islamismus verweist auf eines der schillerndsten und emotional aufgeladensten Themenfelder der letzten zehn bis fünfzehn Jahre. Derzeit ließe sich vermutlich kein zweites finden, dem ein ähnlich großes Interesse seitens der Medien, Politik und Wissenschaft gleichermaßen zukommt. So ist in Deutschland die Rede von jungen Islamisten allgegenwärtig. Doch was genau verbirgt sich überhaupt hinter dem Begriff Islamismus und sind die Hinweise auf junge Islamisten wissenschaftlich fundiert? Der Autor der vorliegenden Untersuchung widmet sich diesen Fragen aus religionswissenschaftlicher Perspektive. Er nimmt hierzu unterschiedliche Verwendungen des Begriffes Islamismus in den Blick und analysiert empirische Studien, die sich mit Islamismus bei Jugendlichen in Deutschland beschäftigen

Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2022

Non peer reviewe

Powerline Communication System-on-Chip in 180 nm Harsh Environment SOI Technology

Broadband powerline communication systems using Orthogonal Frequency Division Multiplexing (OFDM) can utilize existing power lines to transmit data packets alongside power distribution. Recent standards focus towards high speed multi-media in-house streaming. With improvements towards robustness and throughput new standards increase the speed and reliability of in-house powerline systems. A very different approach is the use of powerline communication systems in a deep drilling environment where temperatures of more than 150°C and pressure levels up to 30 000 psi are present. Typical applications in this environment usually do not require more than several kbit/ys per node and are more reliant on a stable and continuous connection. Here, a powerline communication system can reduce the amount of wiring needed and increase communication robustness significantly. This work provides a harsh environment suitable, reliable and standard compliant communication ASIC that is manufactured in XFAB 180 nm Silicon-On-Insulator (SOI) technology allowing operating temperatures of up to 175°C. The die size is 5.25 mm x 5.25 mm and contains a complete Homeplug 1.0 communication stack with an environment for boot, interfacing and debugging. The data rate is as high as 6.1 Mbit/s using the fastest transmission mode and reaches the theoretical maximum of 0.55 Mbit/s in the robust OFDM (ROBO) mode which is of particular interest for harsh environment applications. To the best of the authors knowledge, this is the first OFDM-based powerline communication ASIC which is particularly designed for harsh environment.© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works

Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to μA range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY’ of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2- MOSFET circuits able to implement CARRY’, NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL ADDER implemented using standard cells in the same 0.6 μm CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating gate circuits

D-latch for Subthreshold Floating-Gate Circuits Exploiting Threshold Elements

When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.STC - Sensible Things that Communicat

Trade-offs for high yield in 90 nm subthreshold floating-gate circuits by Monte Carlo simulations

The work described in this paper is performed toestimate the influence of statistical process variations andtransistor mismatch that occurs in fabrication and affectfloating-gate digital circuits. These effects will affect and reduce“yield” (percentage of fully functional circuits). Monte Carlosimulations have been performed in a 90 nm to estimate theyield for manufactured floating-gate circuits running withsubthreshold power supply. The power supply, floating-gatecharge voltage (VFGP and VFGN) and transistor sizes have beenvaried during the simulations and the yield has been observed.The simulation results shows that by doubling the minimumsize transistors (length and width) the yield can be much betterthan for minimum size version. A yield of 100% can though notbe expected if the power supply is scaled down below 250 mV.  STC - Sensible Things that Communicat

The problem of Polyomino tilings number

Darbā ir atrisināta n-salikumu problēma vienkāršākajiem polimino: domino, trimino, tetramino, kā arī doti daži vispārinājumi.The n-tilings problem for simplest polyominoes: domino, tromino, tetromino has been solved in this Bachelor thesis. Some generalizations have been given

Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold

For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.STC - Sensible Things that Communicat